Abstract is missing.
- Chairman's introductionEdwin B. Hassler Jr.. 1 [doi]
- Keynote speakerJerrier A. Haddad. 2 [doi]
- The evolution of design automation to meet the challanges of VLSILawrence M. Rosenberg. 3-11 [doi]
- A generalized channel routerDavid W. Hightower, Robert L. Boyd. 12-21 [doi]
- A "grid-free" channel routerKoji Sato, Hiroyoshi Shimoyama, Takao Nagai, Masaru Ozaki, Toshihiko Yahara. 22-31 [doi]
- An over-the-cell routerDavid N. Deutsch, Paul Glick. 32-39 [doi]
- Design automation at a large architect-engineerE. F. Chelotti, D. P. Bossie. 40-49 [doi]
- System facilities for CAD databasesCharles M. Eastman. 50-56 [doi]
- Weaknesses of commercial data base management systems in engineering applicationsThomas Sidle. 57-61 [doi]
- A new test pattern generation systemYacoub M. El-Ziq. 62-68 [doi]
- Fault diagnosis based on effect-cause analysis: An introductionMiron Abramovici, Melvin A. Breuer. 69-76 [doi]
- Test generation costs analysis and projectionsPrabhakar Goel. 77-84 [doi]
- Issues in IC implementation of high level, abstract designsJin H. Kim, Daniel P. Siewiorek. 85-91 [doi]
- A layout system for the random logic portion of MOS LSIIsao Shirakawa, Noboru Okuda, Takashi Harada, Sadahiro Tani, Hiroshi Ozaki. 92-99 [doi]
- Automation of design for uncommitted logic arrayFrank R. Ramsay. 100-107 [doi]
- The standard transistor array (STAR): Part I A two-layer metal semicustom design systemJohn M. Gould, Teddy M. Edge. 108-113 [doi]
- Inter-active graphic methods for automating mechanical engineering design and analysesJacob M. Miller. 114-128 [doi]
- Computer-aided assignment of manufacturing tolerancesArvind M. Patel. 129-133 [doi]
- Automation of sheet metal design and manufacturingDavid W. Currier. 134-138 [doi]
- Verification of timing constraints on large digital systemsThomas M. McWilliams. 139-147 [doi]
- The SLIDE simulator: A facility for the design and analysis of computer interconnectionsArthur H. Altman, Alice C. Parker. 148-155 [doi]
- Developments in verification of design correctness (A Tutorial)Wendell E. Cory, William M. van Cleemput. 156-164 [doi]
- A survey of space allocation algorithms in use in architectural design in the past twenty yearsRobert Simpson Frew. 165-174 [doi]
- Digital test generation and design for testabilityJohn Grason, Andrew W. Nagle. 175-189 [doi]
- SCOAP: Sandia controllability/observability analysis programLawrence H. Goldstein, Evelyn L. Thigpen. 190-196 [doi]
- The design and implementation of fault insertion capabilities for ISPSJ. Duane Northcutt. 197-209 [doi]
- An accurate functional level concurrent fault simulatorManuel A. d'Abreu, Edward W. Thompson. 210-217 [doi]
- An integrated CAD system for architectureB. T. David. 218-225 [doi]
- A prestructuring model for system arrangement problemsKeiichi Sato, Charles L. Owen. 226-236 [doi]
- A data structure for interactive placement of rectangular objectsV. Jayakumar. 237-242 [doi]
- A line-expansion algorithm for the general routing problem with a guaranteed solutionWalter Heyns, Willy Sansen, Herman Beke. 243-249 [doi]
- A fast maze router with iterative use of variable search space restrictionFumiya Tada, Kiyoshi Yoshimura, Takashi Kagata, Takeyoshi Shirakawa. 250-254 [doi]
- An implementation of a saturated zone multi-layer printed circuit board routerMichael J. Lorenzetti, Robert J. Smith II. 255-262 [doi]
- Design integrity and immunity checking: A new look at layout verification and design rule checkingEdward J. McGrath, Telle Whitney. 263-268 [doi]
- A hierarchical approach for layout versus circuit consistency checkShiu-Ping Chao, Yen-Son Huang, Lap Man Yam. 269 [doi]
- A hierarchical approach for layout versus circuit consistency checkShiu-Ping Chao, Yen-Son Huang, Lap Man Yam. 270-276 [doi]
- An integrated mask artwork analysis systemTakashi Mitsuhashi, Toshiaki Chiba, Makoto Takashima, Kenji Yoshida. 277-284 [doi]
- An IC design station needs a high performance color graphic displayNeil Weste, Bryan D. Ackland. 285-291 [doi]
- SIDS (A Symbolic Interactive Design System)Dave Clary, Robert Kirk, Steve Sapiro. 292-295 [doi]
- Interactive wiring systemFrank D. Skinner. 296-308 [doi]
- Optimization of the influence of problem modifications on given microprogrammed controllersGĂĽnter Biehl, Werner Grass, P. S. Hall. 309-317 [doi]
- Alex: A conversational, hierarchical logic design systemKeith A. Duke, Klim Maling. 318-327 [doi]
- Verifying deep logic hierarchies with ALEXGeorge M. Koppelman, Klim Maling. 328-335 [doi]
- Design automation and VLSI in the 80's (Panel Discussion)Carl R. McCaw. 336-337 [doi]
- A contemporary perspective on design automation and VLSI in the 80's (Position Statement)Jonathan Allen. 338-339 [doi]
- Design automation trends for VLSI in the 1980s (Position Statement)Charles W. Gwyn. 340 [doi]
- Design automation and VLSI in the 80's (Position Statement)R. M. Jacobs. 341 [doi]
- Design tools for VLSI (Position Statement)Benjamin Lee. 342 [doi]
- The VLSI design challenge of the 80's (Position Statement)A. Richard Newton. 343-344 [doi]
- VLSI - a challenge for system designers (Position Statement)Martin B. Roberts. 345 [doi]
- Desisn automation and VLSI in the 80's (Position Statement)Steve Sapiro. 346-347 [doi]
- The management of engineering changes using the PRIMUS systemFelix P. Mallmann. 348-361 [doi]
- An interactive test data system for LSI production testingH. D. Schnurmann, R. M. Peters. 362-366 [doi]
- A tool to support design automation in batch manufacturingGregory L. Smith, Sharon A. Stephens, Leonard L. Tripp, Wayne L. Warren. 367-373 [doi]
- High-speed concurrent fault simulation with vectors and scalarsErnst Ulrich, D. Lacy, N. Phillips, J. Tellier, M. Kearney, T. Elkind, R. Beaven. 374-380 [doi]
- An optimized ATPGSamiha Mourad. 381-385 [doi]
- Methods for generalized deductive fault simulationNorbert Giambiasi, A. Miara, D. Muriach. 386-392 [doi]
- The incorporation of functional level element routines into an existing digital simulation systemEdward W. Thompson, Patrick G. Karger, W. R. Read Jr., Don Ross, John Smith, Richard von Blucher. 394-401 [doi]
- The complexity of design automation problemsSartaj Sahni, Atul Bhatt. 402-411 [doi]
- Complexity theory and design automationWilm E. Donath. 412-419 [doi]
- Design process analysis: A measurement and analysis techniqueKenneth D. Yates. 420-421 [doi]
- The electronics engineer's design stationD. E. Bering. 422-429 [doi]
- An Interactive Graphics System for custom designP. Carmody, A. M. Barone, J. K. Morrell, A. Weiner, John L. Hennessy. 430-439 [doi]
- Technical documentation by "MAGIC" (Machine Aided Graphics for Illustration and CompositionJohn B. Macdonald, Mary K. Podlecki, Milt J. Pappas. 440-445 [doi]
- The use of graphics processors for circuit design simulation at GTE AE LabsJoe Dyer, Arijit Laha, Ernest J. Moran, William D. Smart. 446-450 [doi]
- The Standard Transistor Array (star) (Part II automatic cell placement techniques)Glenn W. Cox, B. D. Carroll. 451-457 [doi]
- Efficient placement and routing techniques for master slice LSIHiroshi Shiraishi, Fumiyasu Hirose. 458-464 [doi]
- Comet - a fast component placerValerie K. Smith, Robert J. Smith II, Phil A. Preston. 465-471 [doi]
- Gate assignment and pack placement: Two approaches comparedFrank Luebbert, Mike Ulrey. 472-482 [doi]
- Algebraic analysis of nondeterministic behaviorSany M. Leinwand, T. Lamdan. 483-493 [doi]
- Detecting bridging and stuck-at faults at input and output pins of standard digital componentsMark G. Karpovsky, Stephen Y. H. Su. 494-505 [doi]
- Automatic design with dependence graphsAlbert E. Casavant, Daniel D. Gajski, David J. Kuck. 506-515 [doi]
- The real world of design automation - part III or The user's viewpoint chairman's introduction (Panel Discussion)Paul Losleben. 516 [doi]
- A CAD user's perspective what gets done right wrong and not at all (Position Paper)R. A. Armstrong. 517 [doi]
- Will your bridge stand the load? (Position Paper)A. E. Fitch. 518 [doi]
- Observations of a CAD user (Position Paper)D. J. Garvin. 519 [doi]
- An automatic routing system for high density multilayer printed wiring boardsIkuo Nishioka, Takuji Kurimoto, Hisao Nishida, Seiji Yamamoto, Toru Chiba, Toshiaki Nagakawa, Takatsugu Fujioka, Masashi Uchino. 520-527 [doi]
- The interchange algorithms for circuit placement problemsL. C. Cote, Arvind M. Patel. 528-534 [doi]
- The genealogical approach to the layout problemAntoni A. Szepieniec, Ralph H. J. M. Otten. 535-542 [doi]
- A new look at logic synthesisJohn A. Darringer, William H. Joyner Jr.. 543-549 [doi]
- Combinational logic synthesis from an HDL descriptionSajjan G. Shiva. 550-555 [doi]
- Practical automated design of LSI for large computersJ. Philip Singleton, Nigel R. Crocker. 556-559 [doi]
- Table lookup techniques for fast and flexible digital logic simulationErnst Ulrich. 560-563 [doi]
- Justification and financial analysis for CADR. E. Powell. 564-571 [doi]
- A prototyping and simulation approach to interactive computer system designPaul R. Hanau, David R. Lenorovitz. 572-578 [doi]
- Selecting and successfully implementing a turnkey computer graphics systemFrank Bliss, George M. Hyman. 579-584 [doi]
- A hierarchical bit-map format for the representation of IC mask dataJames A. Wilmore. 585-589 [doi]
- Cell map representation for hierarchical layoutJirĂ Soukup, J. Royle. 591-594 [doi]
- SLIM-the translation of symbolic layouts into mask dataAlfred E. Dunlop. 595-602 [doi]
- A data structure for gridless routingUlrich Lauther. 603-609 [doi]
- A multiple delay simulator for MOS LSI circuitsHao N. Nham, Ajoy K. Bose. 610-617 [doi]
- A mixed-mode simulatorVishwani D. Agrawal, Ajoy K. Bose, Patrick Kozak, Hao N. Nham, Ernesto Pacas-Skewes. 618-625 [doi]
- MIXS: A mixed level simulator for large digital system logic verificationTohru Sasaki, Akihiko Yamada, Shunichi Kato, Terufumi Nakazawa, Kyoji Tomita, Nobuyoshi Nomizu. 626-633 [doi]
- Functional level simulation at RaytheonDan C. Nash, Keith Russell, Paul Silverman, Mary Thiel. 634-641 [doi]
- Position statement - CAD for VLSISam Bala Daram. 642 [doi]