Table of Contents

• A survey of the state-of-the-art of design automation an invited presentationMelvin A. Breuer. 1 [doi]
• Robotics: The new automation toolHarold R. Marcotte. 2-8 [doi]
• Design for testabilityThomas W. Williams. 9 [doi]
• A retrospective on software engineering in design automationLawrence A. O'Neill. 10-14 [doi]
• Designer's Workbench: Delivery of cad toolsRobert Alan Friendenson, J. R. Breiland, T. J. Thompson. 15-22 [doi]
• A utilitarian approach to CADT. J. Thompson. 23-29 [doi]
• An analytical method for compacting routing area in integrated circuitsMaciej J. Ciesielski, Edwin Kinnen. 30-37 [doi]
• Optimal single row routerRaghunath Raghavan, Sartaj Sahni. 38-45 [doi]
• A new two-dimensional routing algorithmChi-Ping Hsu. 46-50 [doi]
• The Yorktown Simulation Engine: IntroductionGregory F. Pfister. 51-54 [doi]
• The Yorktown Simulation EngineMonty Denneau. 55-59 [doi]
• Software support for the Yorktown Simulation EngineE. Kronstadt, Gregory F. Pfister. 60-64 [doi]
• A logic simulation machineMiron Abramovici, Ytzhak H. Levendel, Premachandran R. Menon. 65-73 [doi]
• Workshop - industrial roboticsHriday R. Prasad. 74 [doi]
• IBM 3081 system overview and technologyClive A. Collins. 75-82 [doi]
• Design verification system for large-scale LSI designsMichael Monachino. 83-90 [doi]
• Operational aspects of design automation for the IBM 3081Robert F. Woodward. 91-95 [doi]
• Automated conversion of design data for building the IBM 3081Vincent J. Freund Jr., J. A. Guerin. 96-103 [doi]
• A minimum-impact routing algorithmKenneth J. Supowit. 104-112 [doi]
• The 1-2-3 routing algorithm or the single channel 2-step router on 3 interconnection layersWalter Heyns. 113-120 [doi]
• A consideration of the number of horizontal grids used in the routing of a masterslice layoutMasayuki Terai, Hajime Kanada, Koji Sato, Toshihiko Yahara. 121-128 [doi]
• A bus router for IC layoutMargaret Lie, Chi-Song Horng. 129-132 [doi]
• A depth-first branch-and-bound algorithm for optimal PLA foldingWerner Grass. 133-140 [doi]
• Optimal bipartite folding of PLAJ. R. Egan, C. L. Liu. 141-146 [doi]
• Techniques for programmable logic array foldingGary D. Hachtel, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli. 147-155 [doi]
• A logic minimizer for VLSI PLA designBill Teel, Doran Wilde. 156-162 [doi]
• Philo-a VLSI design systemRichard L. Donze, Jacob Sanders, Michael Jenkins, George Sporzynski. 163-169 [doi]
• Gate matrix layout of random control logic in a 32-bit CMOS CPU chip adaptable to evolving logic designSung-Mo Kang, Robert H. Krambeck, Hung-Fai Stephen Law. 170-174 [doi]
• A linear-time heuristic for improving network partitionsCharles M. Fiduccia, Robert M. Mattheyses. 175-181 [doi]
• Automated partitioning of hierarchically specified digital systemsThomas S. Payne, William M. van Cleemput. 182-192 [doi]
• Interactive design language: A unified approach to hardware simulation, synthesis and documentationLeon I. Maissel, Daniel L. Ostapko. 193-201 [doi]
• The conlan project: Status and future plansRobert Piloty, Dominique Borrione. 202-212 [doi]
• VHSIC HDLJames B. Rawlings. 213 [doi]
• Evolution of the engineering design system data baseJere L. Sanborn. 214-218 [doi]
• Hardware support for automatic routingErik Damm, H. Gethöffer, K. Kaiser. 219-223 [doi]
• Global wiring on a wire routing machineRavi Nair, Se June Hong, Sandy Liles, Ray Villani. 224-231 [doi]
• A hardware assisted design rule check architectureLarry Seiler. 232-238 [doi]
• Toward CAM-oriented CADFarhad Arbab, Larry Lichten, Michel A. Melkanoff. 239-245 [doi]
• A layout system for high precision design of progressive dieKazuyuki Inoue, Masahiko Adachi, Toru Funayama. 246-252 [doi]
• The planar package planner for system designersWilliam R. Heller, Gregory B. Sorkin, Klim Maling. 253-260 [doi]
• Automatic floorplan designRalph H. J. M. Otten. 261-267 [doi]
• A database management system for design engineersJack Bennett. 268-273 [doi]
• A database approach for managing VLSI design dataRandy H. Katz. 274-282 [doi]
• A low cost, transportable, data management system for LSI/VLSI designDavid C. Smith, Barry S. Wagner. 283-290 [doi]
• Aw expanded logic equation list for checkoutRobert P. Larsen, James Allen Luisi, A. K. Singh. 291-299 [doi]
• PAOLA: A tool for topological optimization of large PLASSamuel Chuquillanqui, Tomás Pérez Segovia. 300-306 [doi]
• A layout synthesis system for NMOS gate-cellsJoseph F. P. Luhukay, William J. Kubitz. 307-314 [doi]
• A functional level modelling language for digital simulationP. J. DesMarais, E. S. Y. Shew, Philip S. Wilcox. 315-320 [doi]
• Modular description/simulation/synthesis using DDLSajjan G. Shiva, J. A. Covington. 321-329 [doi]
• A hardware description language for processor based digital systemsJames H. Tracey, Kovvali Surya Kumar. 330-337 [doi]
• Special purpose vs. general purpose hardware for daT. H. Bruggere. 338 [doi]
• Towards VLSI complexity: The DA algorithm scaling problem: can special DA hardware help?H. G. Adshead. 339-344 [doi]
• The excell method for efficient geometric access to dataMarkku Tamminen, Reijo Sulonen. 345-351 [doi]
• The quad-CIF tree: A data structure for hierarchical on-line algorithmsGershon Kedem. 352-357 [doi]
• Object data structures towards distributed graphics processingDavid Grabel. 358-364 [doi]
• SAGA: An Experimental Silicon AssemblerAntoni A. Szepieniec. 365-370 [doi]
• Riot - a simple graphical chip assembly toolStephen Trimberger, James A. Rowson. 371-376 [doi]
• Designing gate arrays using a silicon compilerJohn P. Gray, Irene Buchanan, Peter S. Robertson. 377-383 [doi]
• Testing functional faults in VLSIYinghua Min, Stephen Y. H. Su. 384-392 [doi]
• A fault simulation methodology for VLSIJohn P. Hayes. 393-399 [doi]
• A fault simulator for MOS LSI circuitsAjoy K. Bose, Patrick Kozak, Chi-Yuan Lo, Hao N. Nham, Ernesto Pacas-Skewes, Kwok W. Wu. 400-409 [doi]
• Design automation algorithms: Research and applicationsRichard J. Lipton, J. D. Nash. 410 [doi]
• Parametric pattern routerTetsuo Asano. 411-417 [doi]
• A "greedy" channel routerRonald L. Rivest, Charles M. Fiduccia. 418-424 [doi]
• An efficient variable-cost maze routerRobert K. Korn. 425-431 [doi]
• Automated rip-up and reroute techniquesWilliam A. Dees Jr., Patrick G. Karger. 432-439 [doi]
• Important criteria in selecting engineering work stationsFontaine Richardson. 440-444 [doi]
• Experiments using interactive color raster graphics for CADAbe R. Shliferstein. 445-452 [doi]
• Design of command menus for CAD systemsLynne A. Price. 453-459 [doi]
• A symbolic design system for integrated circuitsKenneth H. Keller, A. Richard Newton, S. Ellis. 460-466 [doi]
• ALI: A procedural language to describe VLSI layoutsRichard J. Lipton, Stephen C. North, Robert Sedgewick, Jacobo Valdes, Gopalakrishnan Vijayan. 467-474 [doi]
• The "PI" (placement and interconnect) systemRonald L. Rivest. 475-481 [doi]
• Electronic Chip-in-Place TestPrabhakar Goel, M. T. McMahon. 482-488 [doi]
• An enhancement of lssd to reduce test pattern generation effort and increase fault coverageKewal K. Saluja. 489-494 [doi]
• Verification testingEdward J. McCluskey. 495-500 [doi]
• Modeling polyhedral solids bounded by multi-curved parametric surfacesYehuda E. Kalay. 501-507 [doi]
• A user interface for architectural design, a case studyGregory John Glass. 508-513 [doi]
• Design of a graphic processor for computer-aided draftingClive K. Liu, Charles M. Eastman. 514-520 [doi]
• An interactive drafting system based on two dimensional primitivesG. Cosmai, Umberto Cugini, Piero Mussio, Amri Napolitano. 521-529 [doi]
• Lyra: A new approach to geometric layout rule checkingMichael H. Arnold, John K. Ousterhout. 530-536 [doi]
• Cellular image processing techniques for VLSI circuit layout validation and routingTrevor N. Mudge, Rob A. Rutenbar, Robert M. Lougheed, Daniel E. Atkins. 537-543 [doi]
• Programs for verifying circuit connectivity of mos/lsi mask artworkMakoto Takashima, Takashi Mitsuhashi, Toshiaki Chiba, Kenji Yoshida. 544-550 [doi]
• A "non-restrictive" artwork verification program for printed circuit boardsDavid Kaplan. 551-558 [doi]
• DORA: : CAD interface to automatic diagnosticsR. W. Allen, M. M. Ervin-Willis, Rodham E. Tulloss. 559-565 [doi]
• Automatic generation of microprocessor test programsCatherine Bellon, A. Liothin, S. Sadier, Gabriele Saucier, Raoul Velazco, Francois Grillot, M. Issenman. 566-573 [doi]
• Test generation for programmable logic arraysPradip Bose, Jacob A. Abraham. 574-580 [doi]
• An interactive testability analysis program - ITTAPDeepak K. Goel, Robert M. McDermott. 581-586 [doi]
• Speed and accuracy in digital network simulation based on structural modelingErnst Ulrich, Dennis Hebert. 587-593 [doi]
• Timing Verification and the Timing Analysis programRobert B. Hitchcock Sr.. 594-604 [doi]
• Developments in logic network path delay analysisLionel Bening, Thomas A. Lane, Curtis R. Alexander, James E. Smith. 605-615 [doi]
• Auto-delay: A program for automatic calculation of delay in LSI/VLSI chipsRathin Putatunda. 616-621 [doi]
• Timing verification system based on delay time hierarchical natureMinoru Nomura, Shinichi Sato, Nobuo Takano, Toshinori Aoyama, Akihiko Yamada. 622-628 [doi]
• Synchronous path analysis in MOS circuit simulatorVishwani D. Agrawal. 629-635 [doi]
• Simplified data structure for "mini-based" turnkey CAD systemsJoseph Peled. 636-642 [doi]
• A hybrid CAD/CAM system for mechanical applicationsJeffrey Z. Gingerich, Michael P. Carroll, E. J. Chelius, Po-Kuan Lu. 643-649 [doi]
• Making the wire frame solidDonald Robbins. 650-654 [doi]
• A placement algorithm for polycell LSI and ITS evaluationTakashi Kambe, Toru Chiba, Seiji Kimura, Tsuneo Inufushi, Noboru Okuda, Ikuo Nishioka. 655-662 [doi]
• On finding most optimal rectangular package plansKlim Maling, Steven H. Mueller, William R. Heller. 663-670 [doi]
• A combined force and cut algorithm for hierarchical VLSI layoutG. J. Wipfler, Manfred Wiesel, Dieter A. Mlynski. 671-677 [doi]
• Transmission gate modeling in an existing three-value simulatorRobert M. McDermott. 678-681 [doi]
• Relax: A new circuit for large scale MOS integrated circuitsEkachai Lelarasmee, Alberto L. Sangiovanni-Vincentelli. 682-687 [doi]
• Implication algorithms for MOS switch level functional macromodeling implication and testingMichael R. Lightner, Gary D. Hachtel. 691-698 [doi]
• A design system approach to data integrityWilliam A. Noon, Ken N. Robbins, M. Ted Roberts. 699-705 [doi]
• QCADS-a LSI CAD system for minicomputerXian-Long Hong, Ren-kung Yin, Xi-ling Liu. 706-711 [doi]
• A Deterministic finite automaton approach to design rule checking for VLSIR. Alan Eustace, Amar Mukhopadhyay. 712-717 [doi]
• Arbitrarily-sized module location technique in the lop systemGotaro Odawara, Kazuhiko Iijima, Tetsuro Kiyomatsu. 718-726 [doi]
• ICAD/PCB: Integrated computer aided design system for printed circuit boardsHiroshi Shiraishi, Mitsuo Ishii, Shoichi Kurita, Masaaki Nagamine. 727-732 [doi]
• Two-dimensional channel routing and channel intersection problemsManfred Wiesel, Dieter A. Mlynski. 733-739 [doi]
• Defining and implementing a multilevel design representation with simulation applicationsJohn A. Nestor, Donald E. Thomas. 740-746 [doi]
• An Interactive Simulation System for structured logic design - ISSTakeshi Sakai, Yoshiyuki Tsuchida, Hiroto Yasuura, Yasushi Ooi, Yoshitsugu Ono, Hiroshi Kano, Shinji Kimura, Shuzo Yajima. 747-754 [doi]
• Logic simulation for LSIKazuyuki Hirakawa, Noboru Shiraki, Michiaki Muraoka. 755-761 [doi]
• VLSI design methodology workshopJ. D. Nash. 762 [doi]
• Digital logic modeling system based on MODLANAdam Pawlak. 763-770 [doi]
• VEEP A VEctor Editor and PreparerStacey J. Gelman. 771-776 [doi]
• Automated layout in ASHLAR: An approach to the problems of "General Cell" layout for VLSIJames E. Hassett. 777-784 [doi]
• Hierarchical top-down layout design method for VLSI chipTohru Adachi, Hitoshi Kitazawa, Mitsuyoshi Nagatani, Tsuneta Sudo. 785-791 [doi]
• CGALA-a multi technology Gate Array Layout systemLee F. Todd, J. M. Hansen, S. V. Pantulu, John L. Barron, D. J. Gilbert, R. J. Anderson, A. K. Biyani. 792-801 [doi]
• LAMBDA: A quick, low cost layout design system for master-slice LSI sTsuneo Matsuda, Tomyyuki Fujita, K. Takamizawa, H. Mizumura, H. Nakamura, F. Kitajima, Satoshi Goto. 802-808 [doi]
• A formal method for computer design verificationVijay Pitchumani, Edward P. Stabler. 809-814 [doi]
• Formal semantics for the automated derivation of micro-codeRobert A. Mueller, Joseph Varghese. 815-824 [doi]
• Logical correctness by constructionSany M. Leinwand. 825-831 [doi]
• A verification technique for hardware designsFumihiro Maruyama, Takao Uehara, Nobuaki Kawato, Takao Saito. 832-841 [doi]
• Computer system design descriptionYaohan Chu. 842-850 [doi]
• Top down design and testability of VLSI circuitsPhilippe Basset, Gabriele Saucier. 851-857 [doi]
• An interactive logic synthesis system based upon AI techniquesNobuaki Kawato, Takao Uehara, Sadaki Hirose, Takao Saito. 858-864 [doi]
• A language for a scientific and engineering database systemTed M. Sparr. 865-871 [doi]
• A design methodology based upon symbolic layout and integrated cad toolsA. M. Beyls, B. Hennion, Jacques Lecourvoisier, Guy Mazaré, Alain Puissochet. 872-878 [doi]
• Optimum placement of two rectangular blocksMandalagiri S. Chandrasekhar, Melvin A. Breuer. 879-886 [doi]
• On routing for custom integrated circuitsZahir A. Syed, Abbas El Gamal, Melvin A. Breuer. 887-893 [doi]
• On routing two-point nets across a channelRon Y. Pinter. 894-902 [doi]
• Measurements of a VLSI designJohn K. Ousterhout, David M. Ungar. 903-908 [doi]
• Distributed computation for design aidsSaul Yermie Levy. 909-915 [doi]