Tohru Adachi, Hitoshi Kitazawa, Mitsuyoshi Nagatani, Tsuneta Sudo. Hierarchical top-down layout design method for VLSI chip. In James S. Crabbe, Charles E. Radke, Hillel Ofek, editors, Proceedings of the 19th Design Automation Conference, DAC '82, Las Vegas, Nevada, USA, June 14-16, 1982. pages 785-791, ACM/IEEE, 1982. [doi]
Abstract is missing.