Abstract is missing.
- International Test Conference - Cover [doi]
- International Test Conference - Copyright [doi]
- International Test Conference - Title Page [doi]
- Welcoming Message1 [doi]
- Steering Committee and Subcommittees2-3 [doi]
- Ned Kornfield Memorial4 [doi]
- 2003 Paper Awards5 [doi]
- Technical Program Committee6-8 [doi]
- ITC Technical Paper Evaluation and Selection Process10 [doi]
- 2005 Call for Papers11 [doi]
- Test In the Era of What You see Is NOT What You Get Bernd Koenemann. 12 [doi]
- New Test Paradigms for Yield and ManufacturabilityRobert Madge. 13 [doi]
- TTTC: Test Technology Technical Council14-16 [doi]
- Technical Paper Reviewers17-22 [doi]
- AC IO Loopback Design for High Speed µProcessor IO TestBenoit Provost, Chee How Lim, Mo Bashir, Ali Muhtaroglu, Tiffany Huang, Kathy Tian, Mubeen Atha, Cangsang Zhao, Harry Muljono. 23-30 [doi]
- On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance DesignJing Zeng, Magdy S. Abadir, A. Kolhatkar, G. Vandling, Li-C. Wang, Jacob A. Abraham. 31-37 [doi]
- An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance MicroprocessorDavid M. Wu, Mike Lin, Madhukar Reddy, Talal Jaber, Anil Sabbavarapu, Larry Thatcher. 38-47 [doi]
- Efficient Pattern Mapping for Deterministic Logic BISTValentin Gherman, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Michael Garbers. 48-56 [doi]
- Logic BIST with Scan Chain SegmentationLiyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng. 57-66 [doi]
- Spectral Analysis for Statistical Response Compaction During Built-In Self-TestingOmar I. Khan, Michael L. Bushnell. 67-76 [doi]
- A Real-Time Jitter Measurement Board for High-Performance Computer and Communication SystemsTakahiro J. Yamaguchi, Masahiro Ishida, Kiyotaka Ichiyama, Mani Soma, Christian Krawinkel, Katsuaki Ohsawa, Masao Sugai. 77-84 [doi]
- Experimental Results for High-Speed Jitter Measurement TechniqueKaren Taylor, Bryan Nelson, Alan Chong, Hieu Nguyen, Henry C. Lin, Mani Soma, Hosam Haggag, Jeff Huard, Jim Braatz. 85-94 [doi]
- An Automated, Complete, Structural Test Solution for SERDESStephen K. Sunter, Aubin Roy, Jean-Francois Cote. 95-104 [doi]
- A Design for Test Technique for Parametric Analysis of SRAM: On-Die Low Yield AnalysisBenjamin M. Mauck, Vishnumohan Ravichandran, Usman Azeez Mughal. 105-113 [doi]
- Detecting Faults in the Peripheral Circuits and an Evaluation of SRAM TestsA. J. van de Goor, Said Hamdioui, Rob Wadsworth. 114-123 [doi]
- MRAM Defect Analysis and Fault ModeliChin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu. 124-133 [doi]
- CMOS IC diagnostics using the luminescence of OFF-state leakage currentsStas Polonsky, Keith A. Jenkins, Alan J. Weger, Shinho Cho. 134-139 [doi]
- A Novel Scan Chain Diagnostics Technique Based on Light Emission from Leakage CurrentPeilin Song, Franco Stellari, Alan J. Weger, Tian Xia. 140-147 [doi]
- Impact of Negative Bias Temperature Instability on Product Parametric DriftVijay Reddy, John Carulli, Anand T. Krishnan, William Bosch, Brendan Burgess. 148-155 [doi]
- At-Speed Interconnect Test and Diagnosis of External Memories on a SystemHeon C. Kim, Hong Shin Jun, Xinli Gu, Sung Soo Chung. 156-162 [doi]
- Interconnect Test Pattern Generation Algorithm For Meeting Device and Global SSO Limits With Safe Initial VectorsKendrick Baker, Mehrdad Nourani. 163-172 [doi]
- Removing JTAG Bottlenecks in System Interconnect TestHong Shin Jun, Sung Soo Chung, Sang H. Baeg. 173-180 [doi]
- ATE Data Collection - A comprehensive requirements proposal to maximize ROI of testManu Rehani, David Abercrombie, Robert Madge, Jim Teisher, Jason Saw. 181-189 [doi]
- Non-Deterministic DUT Behavior During Functional Testing of High Speed Serial Busses: Challenges and SolutionsJonathan Hops, Brian Swing, Brian Phelps, Bruce Sudweeks, John Pane, James Kinslow. 190-196 [doi]
- Divide and Conquer based Fast Shmoo algorithmsPeter Patten. 197-202 [doi]
- In Search of the Optimum Test Set - Adaptive Test Methods for Maximum Defect Coverage and Lowest Test CostRobert Madge, Brady Benware, Ritesh P. Turakhia, W. Robert Daasch, Chris Schuermyer, Jens Ruffler. 203-212 [doi]
- On Hazard-free Patterns for Fine-delay Fault TestingBram Kruseman, Ananta K. Majhi, Guido Gronthoud, Stefan Eichenberger. 213-222 [doi]
- K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential CircuitsWangqi Qiu, Jing Wang, D. M. H. Walker, Divya Reddy, Zhuo Li, Weiping Shi, Hari Balachandran. 223-231 [doi]
- A Critical Path Selection Method for Delay TestingSaravanan Padmanaban, Spyros Tragoudas. 232-241 [doi]
- Evaluating the Effectiveness of Detecting Delay Defects in the Slack Interval: A Simulation StudyHaihua Yan, Adit D. Singh. 242-251 [doi]
- Quasi-Oscillation Based Test for Improved Prediction of Analog Performance ParametersAshwin Raghunathan, Ji Hwan (Paul) Chun, Jacob A. Abraham, Abhijit Chatterjee. 252-261 [doi]
- On-Chip Impulse Response Generation for Analog and Mixed-Signal TestingAbhishek Singh, Chintan Patel, Jim Plusquellic. 262-270 [doi]
- Automatic Linearity (IP3) Test with Built-in Pattern Generator and AnalyzerFoster F. Dai, Charles E. Stroud, Dayu Yang, Shuying Qi. 271-280 [doi]
- Extending the Digital Core-based Test Methodology to Support Mixed-SignalGeert Seuren, Tom Waayers. 281-289 [doi]
- Systematic Defects in Deep Sub-Micron TechnologiesBram Kruseman, Ananta K. Majhi, Camelia Hora, Stefan Eichenberger, Johan Meirlevede. 290-299 [doi]
- Minimum Testing Requirements to Screen Temperature Dependent DefectsChris Schuermyer, Jens Ruffler, W. Robert Daasch. 300-308 [doi]
- Random and Systematic Defect Analysis Using IDDQ Signature Analysis for Understanding Fails and Guiding Test DecisionsPhil Nigh, Anne E. Gattiker. 309-318 [doi]
- Defect detection under Realistic Leakage Models using Multiple IDDQ MeasurementChintan Patel, Abhishek Singh, Jim Plusquellic. 319-328 [doi]
- Testing Micropipelined Asynchronous CircuitsMatthew L. King, Kewal K. Saluja. 329-338 [doi]
- Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption StandardBo Yang, Kaijie Wu, Ramesh Karri. 339-344 [doi]
- A Holistic Parallel and Hierarchical Approach towards Design-For-TestC. P. Ravikumar, Graham Hetherington. 345-354 [doi]
- Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT TechniquesKenneth M. Butler, Jayashree Saxena, Tony Fryars, Graham Hetherington. 355-364 [doi]
- A New Probing Technique for High-Speed/High-Density Printed Circuit BoardsKenneth P. Parker. 365-374 [doi]
- On-Chip Mixed-Signal Test Structures Re-used for Board TestRodger Schuttert, D. C. L. van Geest, A. Kumar. 375-383 [doi]
- Test Strategy Cost Model InnovationsCarlos Michel, Rosa D. Reinosa. 384-392 [doi]
- Production Test Effectiveness of Combined Automated Inspection and ICT Test StrategiesAmit Verma, Charles Robinson, Steve Butkovich. 393-402 [doi]
- Open Architecture Test System: System Architecture and DesignRochit Rajsuman, Masuda Noriyuki. 403-412 [doi]
- Test Programming Environment in a Modular, Open Architecture Test SystemAnkan K. Pramanick, Ramachandran Krishnaswamy, Mark Elston, Toshiaki Adachi, Harsanjeet Singh, Bruce R. Parnas. 413-422 [doi]
- Extending STIL 1450 Standard for Test Program FlowDavid Dowding, Ernie Wahl, Don Organ. 423-431 [doi]
- X-Tolerant Signature AnalysisSubhasish Mitra, Steven S. Lumetta, Michael Mitzenmacher. 432-441 [doi]
- X-Masking During Logic BIST and Its Impact on Defect CoverageYuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker. 442-451 [doi]
- Channel Masking Synthesis for Efficient On-Chip Test CompressionVivek Chickermane, Brian Foutz, Brion L. Keller. 452-461 [doi]
- CAEN-BIST: Testing the NanoFabricJason G. Brown, R. D. (Shawn) Blanton. 462-471 [doi]
- Fault Tolerant Arithmetic with Applications in Nanotechnology based SystemsWenjing Rao, Alex Orailoglu, Ramesh Karri. 472-478 [doi]
- Routability and Fault Tolerance of FPGA Interconnect ArchitecturesJing Huang, Mehdi Baradaran Tahoori, Fabrizio Lombardi. 479-488 [doi]
- Z-DFD: Design-for-Diagnosability Based on the Concept of Z-DetectionIrith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy. 489-497 [doi]
- Fault Diagnosis in Designs with Convolutional CompactorsGrzegorz Mrugalski, Chen Wang, Artur Pogiel, Jerzy Tyszer, Janusz Rajski. 498-507 [doi]
- Benchmarking Diagnosis Algorithms With a Diverse Set of IC DeformationsThomas J. Vogels, Thomas Zanon, Rao Desineni, R. D. (Shawn) Blanton, Wojciech Maly, Jason G. Brown, Jeffrey E. Nelson, Y. Fei, X. Huang, Padmini Gopalakrishnan, Mahim Mishra, V. Rovner, S. Tiwary. 508-517 [doi]
- An Economic Analysis and ROI Model for Nanometer TestBrion L. Keller, Mick Tegethoff, Thomas Bartenstein, Vivek Chickermane. 518-524 [doi]
- Realizing High Test Quality Goals with Smart Test Resource UsageXinli Gu, Cyndee Wang, Abby Lee, Bill Eklow, Kun-Han Tsai, Jan Arild Tofte, Mark Kassab, Janusz Rajski. 525-533 [doi]
- Low Overhead Delay Testing of ASICSPamela S. Gillis, Francis Woytowich, Andrew Ferko, Kevin McCauley. 534-542 [doi]
- IEEE Std 1149.6 Implementation for a XAUI-to-Serial 10-Gbps TransceiverSaghir A. Shaikh. 543-550 [doi]
- A Frequency Mixing and Sub-Sampling Based RF-Measurement Apparatus for IEEE 1149.4Juha Häkkinen, Pekka Syri, Juha-Veikko Voutilainen, Markku Moilanen. 551-559 [doi]
- Integrating Boundary Scan into Multi-GHz I/O CircuitryJeff Rearick, Sylvia Patterson, Krista Dorner. 560-566 [doi]
- Timing Accuracy Enhancement by a New Calibration Scheme for Multi-Gbps ATEMasashi Shimanouchi. 567-576 [doi]
- Automatic Delay Calibration Method for Multi-channel CMOS FormatterAhmed Rashid Syed. 577-586 [doi]
- Active Tester Interface Unit Design For Data CollectionA. T. Sivaram, Pascal Pierra, Shida Sheibani, Nancy Wang-Lee, Jorge E. Solorzano, Lily Tran. 587-596 [doi]
- SPIN-SIM: Logic and Fault Simulation for Speed-Independent CircuitsFeng Shi, Yiorgos Makris. 597-606 [doi]
- Decision Selection and Learning for an All-Solutions ATPG EngineKameshwar Chandrasekar, Michael S. Hsiao. 607-616 [doi]
- On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential CircuitsJunwu Zhang, Michael L. Bushnell, Vishwani D. Agrawal. 617-626 [doi]
- Localizing Open Interconnect Defects using Targeted Routing in FPGA sDave Mark, Jenny Fan. 627-634 [doi]
- Interconnect Delay Testing of Designs on Programmable Logic DevicesMehdi Baradaran Tahoori, Subhasish Mitra. 635-644 [doi]
- Application-Dependent Diagnosis of FPGAsMehdi Baradaran Tahoori. 645-654 [doi]
- Feed Forward Test Methodology Utilizing Device IdentificationA. Cabbibo, J. Conder, M. Jacobs. 655-660 [doi]
- Data Mining Integrated Circuit Fails with Fail CommonalitiesLeendert M. Huisman, Maroun Kassab, Leah Pastel. 661-668 [doi]
- Evaluation of the Quality of N-Detect Scan ATPG Patterns on a ProcessorEnamul Amyeen, Srikanth Venkataraman, Ajay Ojha, Sangbong Lee. 669-678 [doi]
- Trends in manufacturing test methods and their implicationsSandip Kundu, T. M. Mak, Rajesh Galivanche. 679-687 [doi]
- Trends in Testing Integrated CircuitsBart Vermeulen, Camelia Hora, Bram Kruseman, Erik Jan Marinissen, Robert Van Rijsinge. 688-697 [doi]
- Future Trends in Test: The Adoption and Use of Low Cost Structural TestersAlfred L. Crouch. 698-703 [doi]
- Simulation Based System Level Fault Insertion Using Co-verification ToolsBill Eklow, Anoosh Hosseini, Chi Khuong, Shyam Pullela, Toai Vo, Hien Chau. 704-710 [doi]
- Testing and Remote Field Update of Distributed Base Stations in a Wireless NetworkChen-Huan Chiang, Paul J. Wheatley, Kenneth Y. Ho, Ken L. Cheung. 711-718 [doi]
- IPV6 Conformance Testing: Theory and PracticeYujun Zhang, Zhongcheng Li. 719-727 [doi]
- A High-Throughput 5 GBps Timing and Jitter Test Module Featuring Localized ProcessingMohamed Hafed, Antonio H. Chan, Geoffrey Duerden, Bardia Pishdad, Clarence Tam, Sebastien Laberge, Gordon W. Roberts. 728-737 [doi]
- Tester Architecture For The Source Synchronous BusA. T. Sivaram, Masashi Shimanouchi, Howard Maassen, Robert Jackson. 738-747 [doi]
- Modular Extension of ATE to 5 GbpsDavid C. Keezer, Dany Minier, F. Binette. 748-757 [doi]
- Test Strategies For a 40Gbps Framer SoCHans T. Heineken, Jitendra Khare. 758-763 [doi]
- A Model-based Test Approach for Testing High-Speed PLLs and Phase Regulation Circuitry in SOC DevicesBernd Laquai. 764-772 [doi]
- DFT for Test Optimisations in a Complex Mixed-Signal SOC - Case Study on TI s TNETD7300 ADSL Modem DeviceK. Nikila, Rubin A. Parekhji. 773-782 [doi]
- Delayed-RF Based Test Development for FM Transceivers Using Signature AnalysisErkan Acar, Sule Ozev. 783-792 [doi]
- RF Testing on a Mixed Signal TesterDana Brown, John Ferrario, Randy Wolf, Jing Li, Jayendra Bhagat. 793-800 [doi]
- Use of Embedded Sensors for Built-In-Test of RF CircuitsSoumendu Bhattacharya, Abhijit Chatterjee. 801-809 [doi]
- Formal Verification of a System-on-Chip Using Computation SlicingAlper Sen, Vijay K. Garg, Jacob A. Abraham, Jayanta Bhadra. 810-819 [doi]
- State Variable Extraction to Reduce Problem Complexity for ATPG and Design ValidationQingwei Wu, Michael S. Hsiao. 820-829 [doi]
- Verification on Port ConnectionsGeeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, Chun-Yao Wang. 830-836 [doi]
- Built-In Self-Test for System-on-Chip: A Case StudyCharles E. Stroud, John Sunwoo, Srinivas M. Garimella, Jonathan Harris. 837-846 [doi]
- Hierarchical DFT Methodology - A Case StudyJeff Remmers, Moe Villalba, Richard Fisette. 847-856 [doi]
- A Code-less BIST Processor for Embedded Test and in-system configuration of Boards and SystemsC. J. Clark, Mike Ricchetti. 857-866 [doi]
- Towards Microagent based DBIST/DBISRLiviu Miclea, Szilárd Enyedi, Gavril Toderean, Alfredo Benso, Paolo Prinetto. 867-874 [doi]
- Embedded Test for a new Memory-Card ArchitectureDavid Resnick. 875-882 [doi]
- Concurrent Testing of Droplet-Based Microfluidic Systems for Multiplexed Biomedical AssaysFei Su, Krishnendu Chakrabarty. 883-892 [doi]
- Testing the Configurable Analog Blocks of Field Programmable Analog ArraysTiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Michel Renovell, Marcelo Lubaszewski. 893-902 [doi]
- I/O Self-Leakage TestAli Muhtaroglu, Benoit Provost, Tawfik Rahal-Arabi, Greg Taylor. 903-906 [doi]
- Defect Coverage Analysis of Partitioned TestingSreejit Chakravarty, Eric W. Savage, Eric N. Tran. 907-915 [doi]
- VirtualScan: A New Compressed Scan Technology for Test Cost ReductionLaung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai. 916-925 [doi]
- Data Compression for Multiple Scan Chains Using Dictionaries with CorrectionsArmin Würtenberger, Christofer S. Tautermann, Sybille Hellebrand. 926-935 [doi]
- Improving Encoding Efficiency for Linear Decompressors Using Scan InversionKedarnath J. Balakrishnan, Nur A. Touba. 936-944 [doi]
- Test Cost Reduction Through A Reconfigurable Scan ArchitectureBaris Arslan, Alex Orailoglu. 945-952 [doi]
- Reducing Measurement Uncertainty in a DSP-Based Mixed-Signal Test Environment without Increasing Test TimeChristopher S. Taillefer, Gordon W. Roberts. 953-962 [doi]
- Controlled Sine Wave Fitting for ADC TestHeinz Mattes, Claus Dworski, Sebastian Sattler. 963-971 [doi]
- Precise Pulse Width Measurement in Write Pre-compensation TestHideo Okawara. 972-979 [doi]
- Power Supply Ramping for Quasi-static Testing of PLLsJosé Pineda de Gyvez, Guido Gronthoud, Cristiano Cenci, Martin Posch, Thomas Burger, Manfred Koller. 980-987 [doi]
- Programmable At-Speed Array and Functional BIST for Embedded DRAM LSIMasaji Kume, Katsutoshi Uehara, Minoru Itakura, Hideo Sawamoto, Toru Kobayashi, Masatoshi Hasegawa, Hideki Hayashi. 988-996 [doi]
- A Modular Wrapper Enabling High Speed BIST and Repair for Small Wide MemoriesRobert C. Aitken. 997-1005 [doi]
- AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection ThresholdAndrei Pavlov, Manoj Sachdev, José Pineda de Gyvez. 1006-1015 [doi]
- Post-Packaging Auto Repair Techniques for Fast Row Cycle Embedded DRAMOsamu Wada, Toshimasa Namekawa, Hiroshi Ito, Atsushi Nakayama, Shuso Fujii. 1016-1023 [doi]
- Timing-Independent Testing of Crosstalk in the Presence of Delay Producing Defects Using Surrogate Fault ModelsShahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer. 1024-1033 [doi]
- Identifying Untestable Transition Faults in Latch Based Designs with Multiple ClocksManan Syal, Michael S. Hsiao, Sreejit Chakravarty. 1034-1043 [doi]
- Analysis of delay caused by bridging faults in RLC interconnectsQuming Zhou, Kartik Mohanram. 1044-1052 [doi]
- ALAPTF: A new Transition Faultmodel and the ATPG AlgorithmPuneet Gupta, Michael S. Hsiao. 1053-1060 [doi]
- A Hierarchical DFT Architecture for Chip, Board and System Test/DebugCharles Njinda. 1061-1071 [doi]
- Real Life System Testing of Networking EquipmentSunil Kalidindi, Nghia Huynh, Bill Eklow, Josh Goldstein. 1072-1077 [doi]
- Practical Instrumentation Integration ConsiderationsThomas J. Anderson. 1078-1080 [doi]
- Formal Description of Test Specification and ATE Architecture for Mixed-Signal TestBaolin Deng, Wolfram Glauert. 1081-1090 [doi]
- How to Bridge the Gap Between Simulationand TestMartin Zambaldi, Wolfgang Ecker. 1091-1099 [doi]
- Simulation Requirements for Vectors in ATE FormatsR. Raghuraman. 1100-1107 [doi]
- A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUsBhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi. 1108-1117 [doi]
- Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault TestingRamyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d Abreu. 1118-1127 [doi]
- Speed Clustering of Integrated CircuitsKenneth A. Brand, Erik H. Volkerink, Edward J. McCluskey, Subhasish Mitra. 1128-1137 [doi]
- BER Estimation for Serial Links Based on Jitter Spectrum and Clock Recovery CharacteristicsDongwoo Hong, Chee-Kian Ong, Kwang-Ting (Tim) Cheng. 1138-1147 [doi]
- A High-Resolution Flash Time-to-Digital Converter and Calibration SchemePeter M. Levine, Gordon W. Roberts. 1148-1157 [doi]
- Transfer Functions For The Reference Clock Jitter In A Serial Link: Theory And ApplicationsMike Li, Andy Martwick, Gerry Talbot, Jan B. Wilstrup. 1158-1167 [doi]
- The Leading Edge of Production Wafer Probe Test TechnologyWilliam R. Mann, Frederick L. Taber, Philip W. Seitzer, Jerry J. Broz. 1168-1195 [doi]
- Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-CoresQiang Xu, Nicola Nicolici. 1196-1202 [doi]
- IEEE P1500-Compliant Test Wrapper Design for Hierarchical CoresAnuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty. 1203-1212 [doi]
- An SOC Test Integration Platform and Its Industrial RealizationKuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee. 1213-1222 [doi]
- Risks Associated with Faults within Test Pattern Compactors and Their Implications on TestingCecilia Metra, T. M. Mak, Martin Omaña. 1223-1231 [doi]
- Architectures of Increased Availability Wireless Sensor Network NodesMan Wah Chiang, Zeljko Zilic, Jean-Samuel Chenard, Katarzyna Radecka. 1232-1241 [doi]
- Low Cost Concurrent Error Detection for the Advanced Encryption StandardKaijie Wu, Ramesh Karri, Grigori Kuznetsov, Michael Gössel. 1242-1248 [doi]
- Digital Synchronization for Reconfigurable ATEBurnell G. West, Michael F. Jones. 1249-1254 [doi]
- 34.1Gbps Low Jitter, Low BER High-Speed Parallel CMOS Interface for Interconnections in High-Speed Memory Test SystemDaisuke Watanabe, Masakatsu Suda, Toshiyuki Okayasu. 1255-1262 [doi]
- System Monitor for Diagnostic, Calibration and System ConfigurationMaurizio Gavardoni, Michael Jones, Russell Poffenberger, Miguel Conde. 1263-1268 [doi]
- Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS CircuitsBipul Chandra Paul, Cassondra Neau, Kaushik Roy. 1269-1275 [doi]
- Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault MechanismSebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura, Ali Keshavarzi. 1276-1284 [doi]
- Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault ModelBrady Benware, Cam Lu, John Van Slyke, Prabhu Krishnamurthy, Robert Madge, Martin Keim, Mark Kassab, Janusz Rajski. 1285-1294 [doi]
- Jitter Models and Measurement Methods for High-Speed Serial InterconnectsAndy Kuo, Touraj Farahmand, Nelson Ou, André Ivanov, Sassan Tabatabaei. 1295-1302 [doi]
- Implementation of an Economic Jitter Compliance Test for a Multi-Gigabit Device on ATEGert Hansel, Korbinian Stieglbauer. 1303-1312 [doi]
- Jitter Generation and Measurement for Test of Multigbps Serial IOSassan Tabatabaei, Michael Lee, Freddy Ben-Zeev. 1313-1321 [doi]
- Reducing Power Consumption in Memory ECC CheckersShalini Ghosh, Nur A. Touba, Sugato Basu. 1322-1331 [doi]
- Evaluating the Effects of Transient Faults on Vehicle Dynamic Performance in Automotive SystemsFulvio Corno, Matteo Sonza Reorda, S. Tosato, F. Esposito. 1332-1339 [doi]
- On-line Testing Field Programmable Analog Array CircuitsHaibo Wang, Suchitra Kulkarni, Spyros Tragoudas. 1340-1348 [doi]
- Integrating Core Selection in the SOC Test Solution Design-FlowErik Larsson. 1349-1358 [doi]
- Autonomous Yet Deterministic Test of SOC CoresOzgur Sinanoglu, Alex Orailoglu. 1359-1368 [doi]
- Test Scheduling for Network-on-Chip with BIST and Precedence ConstraintsChunsheng Liu, Hamid Sharif, Érika F. Cota, Dhiraj K. Pradhan. 1369-1378 [doi]
- Testing High Resolution ADCs with Low Resolution/Accuracy Deterministic Dynamic Element Matched DACsHanjun Jiang, Beatriz Olleta, Degang Chen, Randall L. Geiger. 1379-1388 [doi]
- Performance Characterization of Mixed-Signal Circuits Using a Ternary Signal RepresentationHak-soo Yu, Hongjoong Shin, Ji Hwan (Paul) Chun, Jacob A. Abraham. 1389-1397 [doi]
- A Computationally Efficient Method for Accurate Spectral Testing without Requiring Coherent SamplingZhongjun Yu, Degang Chen, Randall L. Geiger. 1398-1407 [doi]
- Open Architecture ATE: Dream or Reality?Gordon D. Robinson. 1408 [doi]
- The Critical Need For Open ATE ArchitectureSergio M. Perez. 1409 [doi]
- Open Architecture ATE: Prospects and ProblemsBurnell G. West. 1410 [doi]
- Security vs. Test Quality: Can We Really Only Have One at a Time?Erik Jan Marinissen. 1411 [doi]
- Electronic circuit comprising a secret sub-moduleHérvé Fleury. 1412 [doi]
- Security vs. Test Quality: Fully Embedded Test Approaches Are the Key to Having BothStephen Pateras. 1413 [doi]
- Security vs. Test Quality: Are they mutually exclusive?Rohit Kapur. 1414 [doi]
- Testing a secure device: High coverage with very low observabilityLaurent Sourgen. 1415 [doi]
- Glamorous Analog Testability - We Already Test them and Ship Them - So What is the Problem?Mohamed Hafed. 1416 [doi]
- 100 DPPM in Nanometer Technology - Is it achievable?Greg Aldrich. 1417 [doi]
- Achieving Sub 100 DPPM Defect Levels on VDSM and Nanometer ASICsBrady Benware. 1418 [doi]
- Sure You Can Get to 100 DPPM in Deep Submicron, But It ll Cost YaKenneth M. Butler. 1419 [doi]
- Achieving Quality Levels of 100dpm: It s possible - but roll up your sleeves and be prepared to do some work.Phil Nigh. 1420 [doi]
- Test Strategies for Nanometer TechnologiesSanjay Sengupta. 1421 [doi]
- Testing in a high volume DSM EnvironmentThomas M. Storey. 1422 [doi]
- What Do You Mean My Board Test Stinks?Bill Eklow. 1423 [doi]
- Functional Test Coverage Effectiveness on the DeclineJay J. Nejedlo. 1424 [doi]
- To Test or To Inspect, What is the Coverage?Rob Jukna. 1425 [doi]
- Board Test Coverage Needs to be StandardizedKenneth P. Parker. 1426 [doi]
- What do you mean my Board Test stinks?Michael J. Smith. 1427 [doi]
- Dude! Where s my data? - Cracking Open the Hermetically Sealed TesterW. Robert Daasch, Manu Rehani. 1428 [doi]
- Redefining ATE: Data Collection Engines that Drive Yield Learning and Process Optimization Phil Nigh. 1429 [doi]
- ATE Value Add through Open Data CollectionRobert Madge. 1430 [doi]
- Cost of Test - Taking ControlNilanjan Mukherjee. 1431 [doi]
- ITC 2004 Panel: Cost of Test - Taking ControlMike Tripp. 1432 [doi]
- Is Design to Production The Ultimate Answer For Jitter, Noise, and BER Challenges For Multi GB/s ICs?Mike Li. 1433 [doi]
- Loopback or not?Takahiro J. Yamaguchi. 1434 [doi]
- Options for High-Volume Test of Multi-GB/s PortsJohn C. Johnson. 1435 [doi]
- Will Heisenberg Uncertainty Principle Hold For Designing and Testing Multiple GB/s ICs?Mike Li. 1436 [doi]
- A Little DFT Goes a Long Way When Testing Multi-Gb/s I/O SignalsJim Sproch. 1437 [doi]
- Panel Synopsis - Diagnosis Meets Physical Failure Analysis: How Long Can We Succeed?Yukio Okuda. 1438 [doi]
- Panel 9 - Diagnostics vs. Failure AnalysisThomas Bartenstein. 1439 [doi]
- Global Failure Localization: We Have To, But on What and How?Edward I. Cole Jr.. 1440 [doi]
- Diagnosis Meets Physical Failure Analysis: How Long can we Succeed?Anne E. Gattiker. 1441 [doi]
- Diagnosis meets Physical Failure Analysis: What is needed to succeed?Srikanth Venkataraman. 1442 [doi]
- How long can we succeed using the OBIRCH and its derivatives ?Kiyoshi Nikawa. 1443 [doi]
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- Plan Ahead for YieldJun Qian. 1447 [doi]