34.1Gbps Low Jitter, Low BER High-Speed Parallel CMOS Interface for Interconnections in High-Speed Memory Test System - researchr publication

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Daisuke Watanabe, Masakatsu Suda, Toshiyuki Okayasu. 34.1Gbps Low Jitter, Low BER High-Speed Parallel CMOS Interface for Interconnections in High-Speed Memory Test System. In Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA. pages 1255-1262, IEEE, 2004. [doi]

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