Table of Contents

• Challenges in Testing Sudhakar M. Reddy. 2 [doi]
• Redundancy Identification Using Transitive ClosureVishwani D. Agrawal, Michael L. Bushnell, Qing Lin. 4-9 [doi]
• Invalid State Identification for Sequential Circuit Test GenerationHsing-Chung Liang, Chung-Len Lee, Jwu E. Chen. 10-15 [doi]
• On Test Generation for Interconnected Finite-State Machines: The Input Sequence Propagation ProblemIrith Pomeranz, Sudhakar M. Reddy. 16-21 [doi]
• Hierarchical Test Generation with Built-In Fault DiagnosisDirk Stroobandt, Jan Van Campenhout. 22-28 [doi]
• Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and RestrictorsJ. Th. van der Linden, M. H. Konijnenburg, A. J. van de Goor. 29-33 [doi]
• E-Groups: A New Technique for Fast Backward Propagation in System Level Test GenerationMichael Nicolaidis, Rubin A. Parekhji, M. Boudjit. 34-41 [doi]
• Efficient Path Delay Fault Test Generation Algorithms for Weighted Random Robust TestingY.-M. Hur, J.-H. Shin, K. H. Lee, Y.-S. Son, I.-C. Lim, Y.-H. Kim. 42 [doi]
• Hybrid Pin Control Using Boundary-Scan And Its ApplicationsWuudiann Ke. 44-49 [doi]
• Hierarchical Testing Using the IEEE Std 1149.5 Module Test and Maintenance Slave Interface ModuleJin-Hua Hong, Chung-Hung Tsai, Cheng-Wen Wu. 50-55 [doi]
• Testing And Diagnosis Of Board Interconnects In Microprocessor-Based SystemsPo-Ching Hsu, Sying-Jyan Wang. 56-61 [doi]
• Syndrome Simulation And Syndrome Test For Unscanned InterconnectsChauchin Su, Shyh-Shen Hwang, Shyh-Jye Jou, Yuan-Tzu Ting. 62-67 [doi]
• A Test Methodology for Interconnect Structures of LUT-based FPGAsHiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara. 68-74 [doi]
• Testable Design and Testing of MCMs Based on Multifrequency ScanWang-Dauh Tseng, Kuochen Wang. 75 [doi]
• A Consistent Scan Design System for Large-Scale ASICsYoshihiro Konno, Kazushi Nakamura, Tatsushige Bitoh, Koji Saga, Seiken Yano. 82-87 [doi]
• A Design for testability Method Using RTL PartitioningToshinori Hosokawa, Kenichi Kawaguchi, Mitsuyasu Ohta, Michiaki Muraoka. 88-93 [doi]
• Partially Parallel Scan Chain for Test Length Reduction by Using Retiming TechniqueYoshinobu Higami, Seiji Kajihara, Kozo Kinoshita. 94-99 [doi]
• Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging FaultsKuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai. 100 [doi]
• On Design of Fail-Safe Cellular ArraysNaotake Kamiura, Yutaka Hata, Kazuharu Yamato. 107-112 [doi]
• Concurrent Error Detection and Fault Location in a Fast ATM SwitchYoon-Hwa Choi, Pong-Gyou Lee. 113-118 [doi]
• Formal Verification Of Self-Testing Properties Of Combinational CircuitsKazuo Kawakubo, Koji Tanaka, Hiromi Hiraishi. 119-122 [doi]
• Constructing an Edge-Route Guaranteed Optimal Fault-Tolerant Routing for Biconnected GraphsYupin Luo, Shiyuan Yang, Dongcheng Hu. 123 [doi]
• An Approach To The Synthesis Of Synchronizable Finite State Machines With Partial ScanTomoo Inoue, Toshimitsu Masuzawa, Hiroshi Youra, Hideo Fujiwara. 130-135 [doi]
• Waveform Polynomial Manipulation Using BddsZhuxing Zhao, Zhongcheng Li, Yinghua Min. 136-141 [doi]
• Easily Testable Data Path Allocation Using Input/Output RegistersLi-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo, Wen-Bin Liao. 142 [doi]
• AND/EXOR based Synthesis of Testable KFDD-Circuits with Small DepthHarry Hengster, Rolf Drechsler, Bernd Becker, Stefan Eckrich, Tonja Pfeiffer. 148 [doi]
• Minimal Delay Test Sets for Unate Gate NetworksUwe Sparmann, H. Mueller, Sudhakar M. Reddy. 155 [doi]
• Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging FaultsKuen-Jong Lee, Jing-Jou Tang. 165-171 [doi]
• Algorithmic Test Generation for Supply Current Testing of TTL Combinational CircuitsToshimasa Kuchii, Masaki Hashizume, Takeomi Tamesada. 171-176 [doi]
• An Efficient Compact Test Generator for IDDQ TestingHisashi Kondo, Kwang-Ting Cheng. 177-182 [doi]
• Realistic Linked Memory Cell Array FaultsA. J. van de Goor, Georgi Gaydadjiev. 183-188 [doi]
• On Current Testing of Josephson Logic Circuits Using the 4JL Gate FamilyTeruhiko Yamada, Tsuyoshi Sasaki. 189 [doi]
• Built-In Self Test for Analog and Mixed-Signal DesignsKwang-Ting Cheng. 197-198 [doi]
• An Efficient PRPG Strategy By Utilizing Essential FaultsLi-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo. 199-204 [doi]
• DP-BIST: A Built-In Self Test For DSP DataPaths A Low Overhead and High Fault Coverage TechniqueSaman Adham, Sanjay Gupta. 205-212 [doi]
• A MISR Computation Algorithm for Fast Signature SimulationBin-Hong Lin, Shao-Hui Shieh, Cheng-Wen Wu. 213-218 [doi]
• BIST Testability Enhancement of System Level Circuits : Experience with An Industrial DesignKowen Lai, Christos A. Papachristou. 219 [doi]
• Low-Complexity Fault Diagnosis Under the Multiple Observation Time Testing ApproachIrith Pomeranz, Sudhakar M. Reddy. 226-231 [doi]
• Efficient Multifrequency Analysis of Fault Diagnosis in Analog Circuits Based on Large Change Sensitivity ComputationTao Wei, Mike W. T. Wong, Y. S. Lee. 232-237 [doi]
• A Practical Implementation Of Dynamic Testing Of An Ad ConverterYuan-Tzu Ting, Li Wei Chao, Wei Chung Chao. 238-243 [doi]
• Comparison Diagnosis in Large Multiprocessor SystemsChristopher P. Fuhrman, Henri J. Nussbaumer. 244 [doi]
• Lessons Learned from Practical Applications of BIST/B-S TechnologyNajmi T. Jarwala, Paul W. Rutkowski, Shianling Wu, Chi W. Yau. 251-257 [doi]
• Yield Improvement by Test Error CancellationJwu E. Chen. 258-262 [doi]
• A Pragmatic, Systematic And Flexible Synthesis For Testability MethodologyVladimir Castro Alves, A. Ribeiro Antunes, Meryem Marzouki. 263-268 [doi]
• A New Model with Time Constraints for Conformance Testing of Communication ProtocolsDaisuke Teratani, Yoshiaki Kakuda, Tohru Kikuno. 269 [doi]
• Test Generation Of Analog Switched-Current CircuitsCheng-Ping Wang, Chin-Long Wey. 276-281 [doi]
• Thermal Monitoring Of Safety-Critical Integrated SystemsVladimir Székely, Márta Rencz, Jean-Michel Karam, Marcelo Lubaszewski, Bernard Courtois. 282-288 [doi]
• A New Scheme For The Fault Diagnosis Of Multiprocessor SystemsXiaofan Yang, Tinghuai Chen, Zehan Cao, Zhongshi He, Hongqing Cao. 289-294 [doi]
• On-Line Testing In Digital Neural NetworksSerge N. Demidenko, Vincenzo Piuri. 295 [doi]