Jin-Fu Lin - researchr alias

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Viewing Publication 1 - 11 from 11

2018

Cross-Domain Hallucination Network for Fine-Grained Object RecognitionJin-Fu Lin, Yen-Liang Lin, Erh-Kan King, Hung-Ting Su, Winston H. Hsu. cvpr 2018: 1214-1221 [doi]

2015

Topology algorithm based on link maintenance time for mobile ad hoc using directional antennasJin-Fu Lin, Peng Bai, Jian Xun Wang, Ying Wang, Tao Wang. ijwmc, 8(3):221-228, 2015. [doi]

2012

A 1-V CDS bandgap reference without on-chip resistorsPeng-Yu Chen, Soon-Jyh Chang, Chung-Ming Huang, Jin-Fu Lin. apccas 2012: 160-163 [doi]

A pipelined SAR ADC with loading-separating technique in 90-nm CMOS technologySheng-Hsiung Lin, Jin-Fu Lin, Guan-Ying Huang, Soon-Jyh Chang. apccas 2012: 264-267 [doi]

2011

Digital Design-for-Diagnosis Method for Error Identification of Pipelined ADCsJin-Fu Lin, Hsin-Wen Ting. et, 27(6):697-709, 2011. [doi]

A Low-Power Mixed-Architecture ADC with Time-Interleaved Correlated Double Sampling Technique and Power-Efficient Back-End StagesJin-Fu Lin, Soon-Jyh Chang. ieicet, 94-C(1):89-101, 2011. [doi]

Transition-Code Based Linearity Test Method for Pipelined ADCs With Digital Error CorrectionJin-Fu Lin, Soon-Jyh Chang, Te-Chieh Kung, Hsin-Wen Ting, Chih-Hao Huang. tvlsi, 19(12):2158-2169, 2011. [doi]

2010

A 10-bit 60-MS/s Low-Power Pipelined ADC With Split-Capacitor CDS TechniqueJin-Fu Lin, Soon-Jyh Chang, Chun-Cheng Liu, Chih-Hao Huang. tcas, 57-II(3):163-167, 2010. [doi]

2009

Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction TechniqueJin-Fu Lin, Soon-Jyh Chang, Chih-Hao Huang. ats 2009: 57-62 [doi]

2008

A Reduced Code Linearity Test Method for Pipelined A/D ConvertersJin-Fu Lin, Te-Chieh Kung, Soon-Jyh Chang. ats 2008: 111-116 [doi]

2006

A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling techniqueJin-Fu Lin, Soon-Jyh Chang. iscas 2006: [doi]

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