Tomonori Sasaki, Yoshiyuki Nakamura, Toshiharu Asaka. Shared At-Speed BIST for Parallel Test of SRAMs with Different Address Sizes. In 17th IEEE Asian Test Symposium, ATS 2008, Sapporo, Japan, November 24-27, 2008. pages 267, IEEE Computer Society, 2008. [doi]
Abstract is missing.