Tomonori Sasaki, Yoshiyuki Nakamura, Toshiharu Asaka. Shared At-Speed BIST for Parallel Test of SRAMs with Different Address Sizes. In 17th IEEE Asian Test Symposium, ATS 2008, Sapporo, Japan, November 24-27, 2008. pages 267, IEEE Computer Society, 2008. [doi]
@inproceedings{SasakiNA08,
title = {Shared At-Speed BIST for Parallel Test of SRAMs with Different Address Sizes},
author = {Tomonori Sasaki and Yoshiyuki Nakamura and Toshiharu Asaka},
year = {2008},
doi = {10.1109/ATS.2008.31},
url = {http://doi.ieeecomputersociety.org/10.1109/ATS.2008.31},
researchr = {https://researchr.org/publication/SasakiNA08},
cites = {0},
citedby = {0},
pages = {267},
booktitle = {17th IEEE Asian Test Symposium, ATS 2008, Sapporo, Japan, November 24-27, 2008},
publisher = {IEEE Computer Society},
isbn = {978-0-7695-3396-4},
}