Table of Contents

• A custom instruction approach for hardware and software implementations of finite field arithmetic over F::2:::63::::: using Gaussian normal basesMarcio Juliato, Guido Araujo, Julio López, Ricardo Dahab. 5-12
• High-Radix Systolic Modular Multiplication on Reconfigurable HardwareCiaran McIvor, Máire McLoone, John V. McCanny. 13-18
• Pipelining Saturated AccumulationKarl Papadantonakis, Nachiket Kapre, Stephanie Chan, André DeHon. 19-26
• A Parameterized Floating-Point Exponential Function for FPGAsJérémie Detrey, Florent de Dinechin. 27-34
• The Erlangen Slot Machine: Increasing Flexibility in FPGA-Based Reconfigurable PlatformsChristophe Bobda, Mateusz Majer, Ali Ahmadinia, Thomas Haller, André Linarth, Jürgen Teich. 37-42
• Task Placement for Heterogeneous Reconfigurable ArchitecturesMarkus Koester, Mario Porrmann, Heiko Kalte. 43-50
• A Framework for Dynamic Resource Assignment and Scheduling on Reconfigurable Mixed-Mode On-Chip MultiprocessorsXiaofang Wang, Sotirios G. Ziavras. 51-58
• High Quality Uniform Random Number Generation Through LUT Optimised Linear RecurrencesDavid B. Thomas, Wayne Luk. 61-68
• Solving the Minimum Dominating Set Problem with Instance-Specific Hardware on FPGAsShin ichi Wakabayashi, Kenji Kikuchi. 69-76
• Custom Hardware Architectures for Posture AnalysisM. P. T. Juvonen, José Gabriel F. Coutinho, J. L. Wang, B. L. Lo, Wayne Luk, Oskar Mencer, G. Z. Yang. 77-84
• Correlation-Based Fingerprint Matching Using FPGAsAlmudena Lindoso, Luis Entrena, Celia López-Ongil, Judith Liu-Jimenez. 87-94
• A Single-Chip FPGA Implementation of Real-Time Adaptive Background ModelKofi Appiah, Andrew Hunter. 95-102
• FPGA-Based Hardware for Physical Modelling Sound Synthesis by Finite Difference SchemesErdem Motuk, Roger Woods, Stefan Bilbao. 103-110
• Have GPUs Made FPGAs Redundant in the Field of Video Processing?Ben Cope, Peter Y. K. Cheung, Wayne Luk, Sarah Witt. 111-118
• S5: The Architecture and Development Flow of a Software Configurable ProcessorJeffrey M. Arnold. 121-128
• RoMultiC: Fast and Simple Configuration Data Multicasting Scheme for Coarse Grain Reconfigurable DevicesVasutan Tunbunheng, Masayasu Suzuki, Hideharu Amano. 129-136
• Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect DelaysShanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita. 137-144
• High-Speed Hardware Architectures of the Whirlpool Hash FunctionMáire McLoone, Ciaran McIvor, Aidan Savage. 147-162
• Secure Partial Reconfiguration of FPGAsAmir Sheikh Zeineddini, Kris Gaj. 155-162
• An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable ProcessorYohei Hasegawa, Shohei Abe, Hiroki Matsutani, Hideharu Amano, Kenichiro Anjo, Toru Awashima. 163-170
• Dynamic Voltage Scaling for Commercial FPGAsC. T. Chow, L. S. M. Tsui, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton. 173-180
• FPGA Architecture for Standby Power ManagementRajarshee P. Bharadwaj, Rajan Konar, Dinesh Bhatia, Poras T. Balsara. 181-188
• FPGA Defect Tolerance: Impact of GranularityAnthony J. Yu, Guy G. Lemieux. 189-196
• A Dynamically Reconfigured UMTS Multi-Channel Complex Code Matched FilterIrwin Kennedy. 199-206
• Prototyping Automatic Cloud Cover Assessment (ACCA) Algorithm for Remote Sensing On-Board Processing on a Reconfigurable ComputerEsam El-Araby, Mohamed Taher, Tarek A. El-Ghazawi, Jacqueline Le Moigne. 207-214
• Reconfigurable Acceleration for Monte Carlo Based Financial SimulationG. L. Zhang, Philip Heng Wai Leong, Chun Hok Ho, Kuen Hung Tsoi, Chris C. C. Cheung, Dong-U Lee, Ray C. C. Cheung, Wayne Luk. 215-222
• Accelerating FPGA Routing Using Architecture-Adaptive A* TechniquesAkshay Sharma, Scott Hauck. 225-232
• Compiler-Directed Design Space Exploration for Caching and Prefetching Data in High-Level SynthesisNastaran Baradaran, Pedro C. Diniz. 233-240
• Post-Silicon Debug Using Programmable Logic CoresBradley R. Quinton, Steven J. E. Wilton. 241-248
• FPGA Organization for the Fast Path-Based Neural Branch PredictorOswaldo Cadenas, Graham M. Megson, Daniel Jones. 251-258
• FPGA Implementation of an Excitatory and Inhibitory Connectionist Model for Motion PerceptionCesar Torres-Huitzil, Bernard Girau. 259-266
• Spatiotemporal Simulation of a Single Living CellYoshiki Yamaguchi, Tsutomu Maruyama, Ryuzo Azuma, Akihiko Konagaya. 267-274
• Dynamic Loading of Peripherals on Reconfigurable System-on-ChipYi Lu 0004, Neil W. Bergmann. 279-280
• An FPGA Model for Developing Dynamic Circuit ComputingTimothy F. Oliver, Douglas L. Maskell. 281-282
• ADH: An Aspect Described Hardware Programming LanguageAndrew Bainbridge-Smith, Su-Hyun Park. 283-284
• From TLM to FPGA: Rapid Prototyping with SystemC and Transaction Level ModelingWolfgang Klingauf, Robert Günzel. 285-286
• Rapid Reconfiguration of an Optically Differential Reconfigurable Gate Array with Pulse LasersMototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi. 287-288
• Hardware-Accelerated SSH on Self-Reconfigurable SystemsIvan Gonzalez, Francisco J. Gomez-Arribas, Sergio López-Buedo. 289-290
• A Fast and Efficient FPGA-Based Implementation for Solving a System of Linear Interval EquationsArvind Sudarsanam, Aravind Dasu. 291-292
• Heuristics for Context-Caches in 2-Level Reconfigurable ArchitecturesSebastian Lange, Martin Middendorf. 293-294
• Performance of Sorting Algorithms on the SRC 6 Reconfigurable ComputerJohn Harkins, Tarek A. El-Ghazawi, Esam El-Araby, Miaoqing Huang. 295-296
• A Zero-Overhead Dynamic Optically Reconfigurable Gate ArrayMinoru Watanabe, Fuminori Kobayashi. 297-298
• The Transmogrifier-4: An FPGA-Based Hardware Development System with Multi-Gigabyte Memory Capacity and High Host and Memory BandwidthJoshua Fender, Jonathan Rose, David R. Galloway. 301-302
• High Performance Channel Model Hardware Emulator for 802.11nAlberto Dassatti, Guido Masera, Mario Nicola, Andrea Concil, Angelo Poloni. 303-304
• HW/SW Interface Synthesis Based on Avalon Bus Specification for Nios-Oriented SoC DesignFeng Lin, Haili Wang, Jinian Bian. 305-306
• A Reconfigurable Architecture for Implementing Multiple Cipher AlgorithmsAli Valizadeh, Morteza Saheb Zamani, Babak Sadeghian, Farhad Mehdipour. 307-308
• Low Latency Elliptic Curve Cryptography Accelerators for NIST Curves Over Binary FieldsChang Shu, Kris Gaj, Tarek A. El-Ghazawi. 309-310
• A System-Level Design Methodology for Reconfigurable Computing ApplicationsEsam El-Araby, Tarek A. El-Ghazawi, Kris Gaj. 311-312
• Optimal FFT Architecture Selection for OFDM Receivers on FPGAMihail Petrov, Manfred Glesner. 313-314
• An FPGA-Based Infant Monitoring SystemPatrick Dickinson, Kofi Appiah, Andrew Hunter, Stephen Ormston. 315-316
• FPGA-Based Conformance Testing and System Prototyping of an MPEG-4 SA-DCT Hardware AcceleratorAndrew Kinane, Alan Casey, Valentin Muresan, Noel E. O Connor. 317-318
• FPGA Core Network Implementation and Optimization: A Case StudyScott Fischaber, R. Hasson, John McAllister, Roger Woods. 319-320
• A State-Serial Viterbi Decoder Architecture for Digital Radio on FPGAMihail Petrov, Manfred Glesner. 323-324
• A Design Methodology to Generate Dynamically Self-Reconfigurable SoCs for Virtex-II Pro FPGAsGerd Van den Branden, Abdellah Touhafi, Erik F. Dirkx. 325-326
• Implementation of Gabor-Type Filters on Field Programmable Gate ArraysOcean Y. H. Cheung, Philip Heng Wai Leong, Eric K. C. Tsang, Bertram Emil Shi. 327-328
• A Scaleable FFT/IFFT Kernel for Communication Systems Using Codesign ApproachP. Potipantong, Theerayod Wiangtong, Phaophak Sirisuk, Apisak Worapishet. 329-330
• FPGA Based Router for Cognitive Packet NetworksLaurence A. Hey, Peter Y. K. Cheung, Michael Gellman. 331-332
• An Overview of High-Level Synthesis of Multiprocessors for Logic ProgrammingAndreas Fidjeland, Wayne Luk. 333-334
• Implementation of EAX Mode of Operation for FPGA Bitstream Encryption and AuthenticationMilind M. Parelkar, Kris Gaj. 335-336
• Net Power Directed Clustering Algorithm for Low Net-Power Implementation of FPGAsSiobhán Launders, Wesley Cooper, Brian Foley. 337-338
• The Design of Scalable Stochastic Biochemical Simulator on FPGAMasato Yoshimi, Yasunori Osana, Yow Iwaoka, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano. 339-340
• Designing an FPGA SoC Using a Standardized IP Block InterfaceLesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow. 341-342