Table of Contents

• BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMsYun-Chao You, Chi-Chun Yang, Jin-Fu Li, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu. 1-6 [doi]
• Dual-Speed TAM Optimization of 3D SoCs for Mid-bond and Post-bond TestingKele Shen, Dong Xiang, Zhou Jiang. 7-12 [doi]
• Optimized Pre-bond Test Methodology for Silicon Interposer TestingKatherine Shu-Min Li, Sying-Jyan Wang, Jia-Lin Wu, Cheng-You Ho, Yingchieh Ho, Ruei-Ting Gu, Bo-Chuan Cheng. 13-18 [doi]
• Design of a Radiation Hardened Latch for Low-Power CircuitsHuaguo Liang, Zhi Wang, Zhengfeng Huang, Aibin Yan. 19-24 [doi]
• Optimal Redundancy Designs for CNFET-Based CircuitsDa Cheng, Fangzhou Wang, Feng Gao, Sandeep K. Gupta. 25-32 [doi]
• A Heuristically Mechanical Model for Accurate and Fast Soft Error AnalysisJiajia Jiao, Yuzhuo Fu. 33-38 [doi]
• Error Resilient Real-Time State Variable Systems for Signal Processing and ControlSuvadeep Banerjee, Alvaro Gómez-Pau, Abhijit Chatterjee, Jacob A. Abraham. 39-44 [doi]
• Variability and Soft-Error Resilience in Dependable VLSI PlatformYukio Mitsuyama, Hidetoshi Onodera. 45-50 [doi]
• Adaptive Mitigation of Parameter VariationsFarshad Firouzi, Fangming Ye, Saman Kiamehr, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori. 51-56 [doi]
• Reliability-Driven Pipelined Scan-Like Testing of Digital Microfluidic BiochipsZipeng Li, Trung Anh Dinh, Tsung-Yi Ho, Krishnendu Chakrabarty. 57-62 [doi]
• A Cost-Effective Stimulus Generator for Battery Channel Characterization in Electric VehiclesShao-Feng Hung, Long-Yi Lin, Hao-Chiao Hong. 63-67 [doi]
• Generator for Test Set Construction of SMGF in Reversible Circuit by Boolean Difference MethodBappaditya Mondal, Dipak Kumar Kole, Debesh Kumar Das, Hafizur Rahaman. 68-73 [doi]
• High-Speed Serial Embedded Deterministic Test for System-on-Chip DesignsMaciej Trawka, Grzegorz Mrugalski, Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jakub Janicki, Jerzy Tyszer. 74-80 [doi]
• A Scalable and Parallel Test Access Strategy for NoC-Based Multicore SystemTaewoo Han, Inhyuk Choi, Hyunggoy Oh, Sungho Kang. 81-86 [doi]
• On Covering Structural Defects in NoCs by Functional TestsAtefe Dalirsani, Nadereh Hatami, Michael E. Imhof, Marcus Eggenberger, Gert Schley, Martin Radetzki, Hans-Joachim Wunderlich. 87-92 [doi]
• Design, Verification, and Application of IEEE 1687Farrokh Ghani Zadegan, Erik Larsson, Artur Jutman, Sergei Devadze, Rene Krenz-Baath. 93-100 [doi]
• Silicon Evaluation of Cell-Aware ATPG Tests and Small Delay TestsFan Yang, Sreejit Chakravarty, Arun Gunda, Nicole Wu, Jianyu Ning. 101-106 [doi]
• On Supporting Sequential Constraints for On-Chip Generation of Post-silicon Validation StimuliXiaobing Shi, Nicola Nicolici. 107-112 [doi]
• Predicting IC Defect Level Using DiagnosisCheng Xue, R. D. Shawn Blanton. 113-118 [doi]
• Testability-Driven Fault Sampling for Deterministic Test Coverage Estimation of Large DesignsKun-Han Tsai. 119-124 [doi]
• Methodology for Early RTL Testability and Coverage Analysis and Its Application to Industrial DesignsChandan Kumar, Fadi Maamari, Kiran Vittal, Wilson Pradeep, Rajesh Tiwari, Srivaths Ravi. 125-130 [doi]
• Circuit Parameter Independent Test Pattern Generation for Interconnect Open DefectsDominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker. 131-136 [doi]
• Built-In Scrambling Analysis for Yield Enhancement of Embedded MemoriesShyue-Kung Lu, Hao-Cheng Jheng, Hao-Wei Lin, Masaki Hashizume, Seiji Kajihara. 137-142 [doi]
• Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMsKuan-Te Wu, Jin-Fu Li, Yun-Chao Yu, Chih-Sheng Hou, Chi-Chun Yang, Ding-Ming Kwai, Yung-Fa Chou, Chih-Yen Lo. 143-148 [doi]
• SRAM Array Yield Estimation under Spatially-Correlated Process VariationJizhe Zhang, Sandeep Gupta. 149-155 [doi]
• Temperature and Voltage Estimation Using Ring-Oscillator-Based Monitor for Field TestYousuke Miyake, Yasuo Sato, Seiji Kajihara, Yukiya Miura. 156-161 [doi]
• On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICsShi-Yu Huang, Hua-Xuan Li, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng. 162-167 [doi]
• A Novel Circuit for Transition-Edge Detection: Using a Stochastic Comparator Group to Test Transition-EdgeTakahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada. 168-173 [doi]
• Low Power Test Compression with Programmable Broadcast-Based ControlSylwester Milewski, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer. 174-179 [doi]
• Exploit Dynamic Voltage and Frequency Scaling for SoC Test Scheduling under Thermal ConstraintsLi Ling, Jianhui Jiang. 180-185 [doi]
• High Quality Testing of Grid Style Power GatingVasileios Tenentes, S. Saqib Khursheed, Bashir M. Al-Hashimi, Shida Zhong, Sheng Yang. 186-191 [doi]
• A Resizing Method to Minimize Effects of Hardware TrojansByeongju Cha, Sandeep K. Gupta. 192-199 [doi]
• High Resolution Pulse Propagation Driven Trojan Detection in Digital Logic: Optimization Algorithms and InfrastructureSabyasachi Deyati, Barry John Muldrey, Adit D. Singh, Abhijit Chatterjee. 200-205 [doi]
• Physically-Aware Diagnostic ResolutionJohn A. Porche, R. D. Shawn Blanton. 206-211 [doi]
• On-Chip Implementation of an Integrator-Based Servo-Loop for ADC Static Linearity TestGuillaume Renaud, Manuel J. Barragan, Salvador Mir, Marc Sabut. 212-217 [doi]
• An ATE Based 32 Gbaud PAM-4 At-Speed Characterization and Testing SolutionJose Moreira, Hubert Werkmann, Masahiro Ishida, Bernhard Roth, Volker Filsinger, Sui-Xia Yang. 218-223 [doi]
• Testing of Non-volatile Logic-Based System ChipsYong-Xiao Chen, Jin-Fu Li. 224-229 [doi]
• Dual-Purpose Mixed-Level Test Generation Using Swarm IntelligenceKelson Gent, Michael S. Hsiao. 230-235 [doi]
• Learning from Production Test Data: Correlation Exploration and Feature EngineeringFan Lin, Chun-Kai Hsu, Kwang-Ting Cheng. 236-241 [doi]
• Perspectives on Test Data Mining from Industrial ExperienceHarry H. Chen. 242-247 [doi]
• Opportunities and Verification Challenges of Run-Time Performance AdaptationMasanori Hashimoto. 248-253 [doi]
• An On-Chip Digital Environment Monitor for Field TestSeiji Kajihara, Yousuke Miyake, Yasuo Sato, Yukiya Miura. 254-257 [doi]
• On-Chip Monitoring for In-Place Diagnosis of Undesired Power Domain Problems in IC ChipsMakoto Nagata, Daisuke Fujimoto, Noriyuki Miura. 258-262 [doi]
• An On-Line Timing Error Detection Method for Silicon DebugYun Cheng, Huawei Li, Xiaowei Li 0001. 263-268 [doi]
• An All Digital Distributed Sensor Network Based Framework for Continuous Noise Monitoring and Timing Failure Analysis in SoCsMehdi Sadi, Zoe Conroy, Bill Eklow, Matthias Kamm, Nematollah Bidokhti, Mark Mohammad Tehranipoor. 269-274 [doi]
• On-Chip Delay Sensor for Environments with Large Temperature FluctuationsJibing Qiu, Guihai Yan, Xiaowei Li 0001. 275-280 [doi]
• Timing Evaluation Tests for Scan Enable Signals with Application to TDF TestingJie Zou, Chao Han, Adit D. Singh. 281-286 [doi]
• FPGA-Based Subset Sum Delay LinesChung-Yun Wang, Yu-Yi Chen, Jiun-Lang Huang, Xuan-Lun Huang. 287-291 [doi]
• Parallel Path Delay Fault Simulation for Multi/Many-Core Processors with SIMD UnitsYussuf Ali, Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue. 292-297 [doi]
• High Quality System Level Test and DiagnosisArtur Jutman, Matteo Sonza Reorda, Hans-Joachim Wunderlich. 298-305 [doi]
• An Efficient Diagnosis Pattern Generation Procedure to Distinguish Stuck-at Faults and Bridging FaultsCheng-Hung Wu, Kuen-Jong Lee. 306-311 [doi]
• On the Generation of Diagnostic Test Set for Intra-cell DefectsZhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Etienne Auvray. 312-317 [doi]
• Diagnosing Cell Internal Defects Using Analog Simulation-Based Fault ModelsHuaxing Tang, Brady Benware, Michael Reese, Joseph Caroselli, Thomas Herrmann, Friedrich Hapke, Robert Tao, Wu-Tung Cheng, Manish Sharma. 318-323 [doi]
• Improving Output Compaction Efficiency with High Observability Scan ChainsSying-Jyan Wang, Che-Wei Kao, Katherine Shu-Min Li. 324-329 [doi]
• Two-Step Dynamic Encoding for Linear DecompressorsEmil Gizdarski. 330-335 [doi]
• A Case Study on Implementing Compressed DFT ArchitectureA. Chandra, S. Chebiyam, R. Kapur. 336-341 [doi]
• Leveraging Emerging Technology for Hardware Security - Case Study on Silicon Nanowire FETs and Graphene SymFETsYu Bi, Pierre-Emmanuel Gaillardon, Xiaobo Sharon Hu, Michael T. Niemier, Jiann-shiun Yuan, Yier Jin. 342-347 [doi]
• Advanced Analysis of Cell Stability for Reliable SRAM PUFsAlison Hosey, Md. Tauhidur Rahman, Kan Xiao, Domenic Forte, Mohammad Tehranipoor. 348-353 [doi]
• On the Use of Scan Chain to Improve Physical Attacks (Extended Abstract)Junfeng Fan, Hua Xie, YiWei Zhang. 354-357 [doi]