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FPGA-Based Subset Sum Delay Lines

Chung-Yun Wang, Yu-Yi Chen, Jiun-Lang Huang, Xuan-Lun Huang. FPGA-Based Subset Sum Delay Lines. In 23rd IEEE Asian Test Symposium, ATS 2014, Hangzhou, China, November 16-19, 2014. pages 287-291, IEEE Computer Society, 2014. [doi]

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