Abstract is missing.
- Something I Always Wanted to Know About Test, But Was Afraid to AskChristian Landrault. [doi]
- We Have Got Compression, What Next?Janusz Rajski. [doi]
- Testing of High Resolution ADCs Using Lower Resolution DACs via Iterative Transfer Function EstimationS. Kook, Vishwanath Natarajan, Abhijit Chatterjee, Shalabh Goyal, Le Jin. 3-8 [doi]
- Speed-Path Debug Using At-Speed Scan Test PatternsRuifeng Guo, Wu-Tung Cheng, Kun-Han Tsai. 11-16 [doi]
- Resource-Efficient Programmable Trigger Units for Post-Silicon ValidationHo Fai Ko, Nicola Nicolici. 17-22 [doi]
- On Minimization of Peak Power for Scan Circuit during TestJaynarayan T. Tudu, Erik Larsson, Virendra Singh, Vishwani D. Agrawal. 25-30 [doi]
- Exploiting Thread-Level Parallelism in Functional Self-Testing of CMT ProcessorsAndreas Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Ishwar Parulkar. 33-38 [doi]
- Doubling Test Cell Throughput by On-Loadboard Hardware- Implementation and Experience in a Production EnvironmentFrank-Uwe Faber, Matthias Beck, Markus Rudack, Olivier Barondeau, Thomas Rabenalt, Michael Gössel, Andreas Leininger. 39-44 [doi]
- Algorithms for ADC Multi-site Test with Digital Input StimulusXiaoqin Sheng, Hans G. Kerkhoff, Amir Zjajo, Guido Gronthoud. 45-50 [doi]
- Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and OverheadMichael A. Kochte, Christian G. Zoellin, Hans-Joachim Wunderlich. 53-58 [doi]
- Design and Test Challenges in Resistive Switching RAM (ReRAM): An Electrical Model for Defect InjectionsOlivier Ginez, Jean Michel Portal, Ch. Muller. 61-66 [doi]
- Novel Solution for the Built-in Gate Oxide Stress Test of LDMOS in Integrated Circuits for Automotive ApplicationsVezio Malandruccolo, Mauro Ciappa, Wolfgang Fichtner, Hubert Rothleitner. 67-72 [doi]
- Built-in Test Solutions for the Electrode Structures in Bio-Fluidic MicrosystemsQ. Al-Gayem, H. Liu, A. Richardson, N. Burd. 73-78 [doi]
- Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning TechniquesStephan Eggersglüß, Rolf Drechsler. 81-86 [doi]
- Input Cubes with Lingering Synchronization Effects and their Use in Random Sequential Test GenerationIrith Pomeranz, Sudhakar M. Reddy. 87-92 [doi]
- Automatic Functional Stress Pattern Generation for SoC Reliability CharacterizationDavide Appello, Paolo Bernardi, R. Cagliesi, M. Giancarlini, Michelangelo Grosso, Edgar E. Sánchez, Matteo Sonza Reorda. 93-98 [doi]
- Defect Filter for Alternate RF TestHaralampos-G. D. Stratigopoulos, Salvador Mir, Erkan Acar, Sule Ozev. 101-106 [doi]
- Signature-Based Testing for Digitally-Assisted Adaptive Equalizers in High-Speed Serial LinksMohamed Abbas, Kwang-Ting Cheng, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada. 107-112 [doi]
- A Two Phase Approach for Minimal Diagnostic Test Set GenerationMohammed Ashfaq Shukoor, Vishwani D. Agrawal. 115-120 [doi]
- Categorizing and Analysis of Activated Faults in the FlexRay Communication Controller RegistersYasser Sedaghat, Seyed Ghassem Miremadi. 121-126 [doi]
- Low-Complexity Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test ChipKihyuk Han, Joonsung Park, Jae-Wook Lee, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo, Sejang Oh. 129-134 [doi]
- A Voltage-Mode Testing Method to Detect IDDQ Defects in Digital CircuitsJosep Rius, Luis Elvira Villagra, Maurice Meijer. 135-140 [doi]
- Partial Scan Approach for Secret Information ProtectionMichiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara. 143-148 [doi]
- Masking of X-values by Use of a Hierarchically Configurable RegisterThomas Rabenalt, Michael Gössel, Andreas Leininger. 149-154 [doi]
- Test Encoding for Extreme Response CompactionMichael A. Kochte, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich. 155-160 [doi]
- Critical Path Selection for Delay Test Considering Coupling NoiseRajeshwary Tayade, Jacob A. Abraham. 163-168 [doi]