Table of Contents

• Fault mitigation strategies for CUDA GPUsStefano Di Carlo, Giulio Gambardella, Ippazio Martella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta. 1-8 [doi]
• ATE test time reduction using asynchronous clock periodPraveen Venkataramani, Vishwani D. Agrawal. 1-10 [doi]
• Accurate full spectrum test robust to simultaneous non-coherent sampling and amplitude clippingSiva Sudani, Li Xu, Degang Chen. 1-10 [doi]
• A functional test of 2-GHz/4-GHz RF digital communication device using digital testerKiyotaka Ichiyama, Masahiro Ishida, Kenichi Nagatani, Toshifumi Watanabe. 1-10 [doi]
• Early-life-failure detection using SAT-based ATPGMatthias Sauer, Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung Tae Do, Jung Yun Choi, Kee Sup Kim, Subhasish Mitra, Bernd Becker. 1-10 [doi]
• Fault diagnosis of TSV-based interconnects in 3-D stacked designsJanusz Rajski, Jerzy Tyszer. 1-9 [doi]
• Diagnosis and Layout Aware (DLA) scan chain stitchingJing Ye, Yu Huang 0005, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li 0001, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan. 1-10 [doi]
• Differential scan-path: A novel solution for secure design-for-testabilitySalvador Manich, Markus S. Wamser, Oscar M. Guillen, Georg Sigl. 1-9 [doi]
• Predicting system-level test and in-field customer failures using data miningHarry H. Chen, Roger Hsu, PaulYoung Yang, J. J. Shyr. 1-10 [doi]
• Fault modeling and diagnosis for nanometric analog circuitsKe Huang, Haralampos-G. D. Stratigopoulos, Salvador Mir. 1-10 [doi]
• VLSI testing based security metric for IC camouflagingJeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri. 1-4 [doi]
• A design-for-reliability approach based on grading library cells for aging effectsSenthil Arasu, Mehrdad Nourani, John M. Carulli, Kenneth M. Butler, Vijay Reddy. 1-7 [doi]
• An enhanced procedure for calculating dynamic properties of high-performance DAC on ATEMing Lu. 1-10 [doi]
• A distributed-multicore hybrid ATPG systemX. Cai, Peter Wohl. 1-7 [doi]
• EDT bandwidth management - Practical scenarios for large SoC designsJakub Janicki, Jerzy Tyszer, W.-T. Cheng, Y. Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Y. Dong, G. Giles. 1-10 [doi]
• Self-repair of uncore components in robust system-on-chips: An OpenSPARC T2 case studyYanjing Li, Eric Cheng, Samy Makar, Subhasish Mitra. 1-10 [doi]
• Counterfeit electronics: A rising threat in the semiconductor manufacturing industryKe Huang, John M. Carulli, Yiorgos Makris. 1-4 [doi]
• Test-yield improvement of high-density probing technology using optimized metal backer with plastic patchSen-Kuei Hsu, Hao Chen, Chung-Han Huang, Der-Jiann Liu, Wei-Hsun Lin, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang. 1-10 [doi]
• Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case studySandeep Kumar Goel, Saman Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, Frank Lee, Vivek Chickermane, Brion L. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Hyungdong Lee, Jungi Choi, Sangdoo Kim. 1-10 [doi]
• The implementation and application of a protocol aware architectureTimothy Lyons, George Conner, John Aslanian, Shawn Sullivan. 1-10 [doi]
• Test time reduction with SATOM: Simultaneous AC-DC Test with Orthogonal Multi-excitationsDegang Chen, Zhongjun Yu, Krunal Maniar, Mojtaba Nowrozi. 1-9 [doi]
• Performance enhancement of a WCDMA/HSDPA+ receiver via minimizing error vector magnitudeWei Gao, Chris Liu. 1-7 [doi]
• Delay testing and characterization of post-bond interposer wires in 2.5-D ICsShi-Yu Huang, Li-Ren Huang, Kun-Han Tsai, Wu-Tung Cheng. 1-8 [doi]
• Theory, model, and applications of non-Gaussian probability density functions for random jitter/noise with non-white power spectral densitiesDaniel Chow, Masashi Shimanouchi, Mike Peng Li. 1-8 [doi]
• Test data analytics - Exploring spatial and test-item correlations in production test dataChun-Kai Hsu, Fan Lin, Kwang-Ting Cheng, Wangyang Zhang, Xin Li, John M. Carulli, Kenneth M. Butler. 1-10 [doi]
• A pattern mining framework for inter-wafer abnormality analysisNik Sumikawa, Li-C. Wang, Magdy S. Abadir. 1-10 [doi]
• SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up statesBen Niewenhuis, R. D. Blanton, Mudit Bhargava, Ken Mai. 1-8 [doi]
• Welcome messageGordon W. Roberts, Rob Aitken. 1 [doi]
• Towards data reliable crossbar-based memristive memoriesAmirali Ghofrani, Miguel Angel Lastras-Montano, Kwang-Ting Cheng. 1-10 [doi]
• FPGA-based universal embedded digital instrumentJoshua Ferry. 1-9 [doi]
• Adaptive testing - Cost reduction through test pattern samplingMatt Grady, Bradley Pepper, Joshua Patch, Michael Degregorio, Phil Nigh. 1-8 [doi]
• Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architecturesHongyan Zhang, Lars Bauer, Michael A. Kochte, Eric Schneider, Claus Braun, Michael E. Imhof, Hans-Joachim Wunderlich, Jörg Henkel. 1-10 [doi]
• A graph-theoretic approach for minimizing the number of wrapper cells for pre-bond testing of 3D-stacked ICsMukesh Agrawal, Krishnendu Chakrabarty. 1-10 [doi]
• 30-Gb/s optical and electrical test solution for high-volume testingDaisuke Watanabe, Shin Masuda, Hideo Hara, Tsuyoshi Ataka, Atsushi Seki, Atsushi Ono, Toshiyuki Okayasu. 1-10 [doi]
• PADRE: Physically-Aware Diagnostic Resolution EnhancementYang Xue, Osei Poku, Xin Li, Ronald D. Blanton. 1-10 [doi]
• Representative critical-path selection for aging-induced delay monitoringFarshad Firouzi, Fangming Ye, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori. 1-10 [doi]
• Design rule check on the clock gating logic for testability and beyondKun-Han Tsai, Shuo Sheng. 1-8 [doi]
• In-system diagnosis of RF ICs for tolerance against on-chip in-band interferersNaoya Azuma, T. Makita, S. Ueyama, Makoto Nagata, S. Takahashi, M. Murakami, K. Hori, S. Tanaka, M. Yamaguchi. 1-9 [doi]
• A circular pipeline processing based deterministic parallel test pattern generatorKuen-Wei Yeh, Jiun-Lang Huang, Hao-Jan Chao, Laung-Terng Wang. 1-8 [doi]
• 12Gbps SerDes Jitter Tolerance BIST in production loopback testing with enhanced spread spectrum clock generation circuitYi Cai, Liming Fang, Ivan Chan, Max Olsen, Kevin Richter. 1-8 [doi]
• Application of under-approximation techniques to functional test generation targeting hard to detect stuck-at faultsMahesh Prabhu, Jacob A. Abraham. 1-7 [doi]
• True non-intrusive sensors for RF built-in testLouay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir. 1-10 [doi]
• AgentDiag: An agent-assisted diagnostic framework for board-level functional failuresZelong Sun, Li Jiang, Qiang Xu, Zhaobo Zhang, Zhiyuan Wang, Xinli Gu. 1-8 [doi]
• RF MEMS switches for Wide I/O data bus applicationsMichael B. Cohn, Kaosio Saechao, Michael Whitlock, Daniel Brenman, Wallace T. Tang, Robert M. Proie. 1-8 [doi]
• Practical methods for extending ATE to 40 and 50GbpsDavid C. Keezer, Carl Edward Gray, Te-Hui Chen, Ashraf Majid. 1-10 [doi]
• SmartScan - Hierarchical test compression for pin-limited low power designsKrishna Chakravadhanula, Vivek Chickermane, D. Pearl, A. Garg, R. Khurana, S. Mukherjee, P. Nagaraj. 1-9 [doi]
• On the generation of compact test setsAmit Kumar, Janusz Rajski, Sudhakar M. Reddy, Chen Wang. 1-10 [doi]
• Zero-overhead self test and calibration of RF transceiversAfsaneh Nassery, Jae-woong Jeong, Sule Ozev. 1-9 [doi]
• Don't forget to lock your SIB: Hiding instruments using P16871Jennifer Dworak, Al Crouch, John C. Potter, Adam Zygmontowicz, Micah Thornton. 1-10 [doi]
• A novel test structure for measuring the threshold voltage variance in MOSFETsTakahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada. 1-8 [doi]
• Two-level compression through selective reseedingPeter Wohl, John A. Waicukauski, Frederic Neuveux, Gregory A. Maston, Nadir Achouri, J. E. Colburn. 1-10 [doi]
• On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMsLeonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine. 1-10 [doi]
• Advanced method to refine waveform smeared by jitter in waveform sampler measurementHideo Okawara. 1-9 [doi]
• BA-BIST: Board test from inside the IC outZoe Conroy, Alfred L. Crouch. 1 [doi]
• Process monitoring through wafer-level spatial variation decompositionKe Huang, Nathan Kupp, John M. Carulli Jr., Yiorgos Makris. 1-10 [doi]
• Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICsSergej Deutsch, Krishnendu Chakrabarty, Erik Jan Marinissen. 1-10 [doi]
• High sensitivity test signatures for unconventional analog circuit test paradigmsSuraj Sindia, Vishwani D. Agrawal. 1-10 [doi]
• Best paper award winnersZ. Yu, D. Chen. 4 [doi]
• Keynote address tuesday: Challenges in mobile devices: Process, design and manufacturingKwang Hyun Kim. 8 [doi]
• Keynote address wednesday: Compute continuum and the nonlinear validation challengeJohn D. Barton. 9 [doi]
• Keynote address thursday: Efficient resilience in future systems: Design and modeling challengesPradip Bose. 10 [doi]