Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures

Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita. Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures. In Achim Rettberg, Mauro Cesar Zanella, Rainer Dömer, Andreas Gerstlauer, Franz-Josef Rammig, editors, Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30 - June 1, 2007, Irvine, CA, USA. Volume 231 of IFIP, pages 121-134, Springer, 2007. [doi]

Abstract

Abstract is missing.