Abstract is missing.
- Executable Computational Logics: Combining Formal Methods and Programming Language Based System DesignJosé Meseguer. 3 [doi]
- MoDe: A Method for System-Level Architecture EvaluationJan Romberg, Oscar Slotosch, Gabor Hahn. 13-23 [doi]
- From Use Cases to System Implementation: Statechart Based Co-designLuís Gomes, Anikó Costa. 24-33 [doi]
- Petri Net Based Interface Analysis for Fast IP-Core IntegrationJulio A. de Oliveira Filho, Manoel Eusebio de Lima, Paulo Romero Martins Maciel. 34 [doi]
- Goal-Oriented Requirements Analysis for Process Control Systems DesignIslam A. M. El-Maddah, T. S. E. Maibaum. 45-46 [doi]
- Analyzing Concurrency in Computational NetworksSander Stuijk, Twan Basten. 47-48 [doi]
- Translating Fusion/UML to Object-ZMargot Bittner, Florian Kammüller. 49-50 [doi]
- Finding Good Counter-Examples to Aid Design VerificationGörschwin Fey, Rolf Drechsler. 51 [doi]
- High Level Verification of Control Intensive Systems Using Predicate AbstractionEdmund M. Clarke, Orna Grumberg, Muralidhar Talupur, Dong Wang. 55-64 [doi]
- Formal Verification of an Intel XScale Processor Model with Scoreboarding, Specialized Execution Pipelines, and Impress Data-Memory ExceptionsSudarshan K. Srinivasan, Miroslav N. Velev. 65-74 [doi]
- Combining ACL2 and a v-calculus Model-Checker to Verify System-Level DesignsMagali Contensin, Laurence Pierre. 75 [doi]
- Engineering Changes in Field Modifiable ArchitecturesHiroshi Saito, Kenshu Seto, Yoshihisa Kojima, Satoshi Komatsu, Masahiro Fujita. 87-94 [doi]
- Hierarchical and Incremental Verification for System Level Design: Challenges and AccomplishmentsGrant Martin, Sandeep K. Shukla. 97 [doi]
- How to Compute the Refinement Relation for Parameterized SystemsFrançoise Bellegarde, Celina Charlet, Olga Kouchnarenko. 103-112 [doi]
- Using SSDE for USB2.0 conformance co-verificationThierry J.-F. Omnés, Gerard Postuma, Jos Verhaegh, Marleen Boonen, Nick Gatherer. 113-122 [doi]
- From Algorithm and Architecture Specifications to Automatic Generation of Distributed Real-Time Executives: a Seamless Flow of Graphs TransformationsThierry Grandpierre, Yves Sorel. 123 [doi]
- Methods for exploiting SAT solvers in unbounded model checkingKenneth L. McMillan. 135 [doi]
- On the Use of a High-Level Fault Model to Check Properties IncompletenessFranco Fummi, Graziano Pravadelli, Andrea Fedeli, Umberto Rossi, Franco Toto. 145-152 [doi]
- Exact Runtime Analysis Using Automata-Based Symbolic SimulationTobias Schüle, Klaus Schneider. 153-162 [doi]
- Real-time Property Preservation in Approximations of Timed SystemsJinfeng Huang, Jeroen Voeten, Marc Geilen. 163-171 [doi]
- Reliability Evaluation for Dependable Embedded System Specifications: An Approach Based on DSPNSérgio M. M. Fernandes, Paulo Romero Martins Maciel. 172 [doi]
- Modular Hierarchies of Models for Embedded SystemsManfred Broy. 183 [doi]
- Verification of Transaction-Level SystemC models using RTL TestbenchesRohit Jindal, Kshitiz Jain. 199-203 [doi]
- LOTOS Code Generation for Model Checking of STBus Based SoC: the STBus interconnectPierre Wodey, Geoffrey Camarroque, Fabrice Baray, Richard Hersemeule, Jean-Philippe Cousin. 204 [doi]
- A Generalised Approach to Supervisor SynthesisRoberto Ziller, Klaus Schneider. 217-226 [doi]
- Optimizations for Faster Execution of Esterel ProgramsDumitru Potop-Butucaru, Robert de Simone. 227-236 [doi]
- Bridging CSP and C++ with Selective Formalism and Executable SpecificationsWilliam B. Gardner. 237 [doi]
- Bluespec: A language for hardware design, simulation, synthesis and verification Invited TalkArvind. 249 [doi]
- A Verification Methodology for Infinite-State Message Passing SystemsChristoph Sprenger, Krzysztof Worytkiewicz. 255-264 [doi]
- Verification of Control Properties in the Polyhedral ModelDavid Cachera, Katell Morin-Allory. 265 [doi]
- Should the space of implementation possibilities be determined by the abilities of high-level synthesis and validation?Rajesh K. Gupta, Sandeep K. Shukla. 277 [doi]
- Robust System Design with Uncertain InformationGiovanni De Micheli. 283 [doi]