Table of Contents

• Classes of difficult-to-diagnose transition fault clustersIrith Pomeranz. 1-6 [doi]
• Mixed structural-functional path delay test generation and compactionKun Bian, D. M. H. Walker, Sunil P. Khatri, Shayak Lahiri. 7-12 [doi]
• A data mining approach to incremental adaptive functional diagnosisCristiana Bolchini, Elisa Quintarelli, Fabio Salice, Paolo Garza. 13-18 [doi]
• An energy-efficient and robust millimeter-wave Wireless Network-on-Chip architectureNaseef Mansoor, Amlan Ganguly, Manoj Prashanth Yuvaraj. 19-24 [doi]
• CFEDR: Control-flow error detection and recovery using encoded signatures monitoringLanfang Tan, Ying Tan, Jianjun Xu. 25-32 [doi]
• A low power architecture for online detection of execution errors in SMT processorsRance Rodrigues, Sandip Kundu. 33-38 [doi]
• SAT-based code synthesis for fault-secure circuitsAtefe Dalirsani, Michael A. Kochte, Hans-Joachim Wunderlich. 39-44 [doi]
• DaemonGuard: O/S-assisted selective software-based Self-Testing for multi-core systemsMichael A. Skitsas, Chrysostomos Nicopoulos, Maria K. Michael. 45-51 [doi]
• A novel scheme for concurrent error detection of OLS parallel decodersKazuteru Namba, Fabrizio Lombardi. 52-57 [doi]
• Run-time mapping for reliable many-cores based on energy/performance trade-offsCristiana Bolchini, Matteo Carminati, Antonio Miele, Anup Das, Akash Kumar, Bharadwaj Veeravalli. 58-64 [doi]
• Analysing degradation effects in charge-redistribution SAR ADCsMuhammad Aamir Khan, Hans G. Kerkhoff. 65-70 [doi]
• A cross-layer fault-tolerant design method for high manufacturing yield and system reliabilityJianghao Guo, Qiang Han, Wen-Ben Jone, Yu-Liang Wu. 71-76 [doi]
• Fault Injection Framework for embedded memoriesPatryk Skoncej. 77-82 [doi]
• A fast TCAD-based methodology for Variation analysis of emerging nano-devicesHassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Majid Yazdani, Giovanni De Micheli. 83-88 [doi]
• Low power and high speed current-mode memristor-based TLGsChandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas. 89-94 [doi]
• Approximate simulation of circuits with probabilistic behaviorAlexandru Paler, Josef Kinseher, Ilia Polian, John P. Hayes. 95-100 [doi]
• Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security-driven task schedulingChen Liu, Jeyavijayan Rajendran, Chengmo Yang, Ramesh Karri. 101-106 [doi]
• F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environmentsStefano Campitelli, Marco Ottavi, Salvatore Pontarelli, Alessandro Marchioro, Daniele Felici, Fabrizio Lombardi. 107-111 [doi]
• Evaluating CLB designs under multiple SETs in SRAM-based FPGAsArwa Ben Dhia, Lirida A. B. Naviner, Philippe Matherat. 112-117 [doi]
• Technology-aware system failure analysis in the presence of soft errors by Mixture Importance SamplingVeit Kleeberger, Daniel Mueller-Gritschneder, Ulf Schlichtmann. 118-124 [doi]
• Efficient compression of x-masking control data via dynamic channel allocationAsad Amin Bawa, Muhammad Tauseef Rab, Nur A. Touba. 125-130 [doi]
• LMS-based RF BIST architecture for multistandard transmittersEmanuel Dogaru, Filipe Vinci dos Santos, William Rebernak. 131-136 [doi]
• Synthesis of workload monitors for on-line stress predictionRafal Baranowski, Alejandro Cook, Michael E. Imhof, Chang Liu, Hans-Joachim Wunderlich. 137-142 [doi]
• On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cellElena I. Vatajelu, Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné. 143-148 [doi]
• Robustness improvement of an SRAM cell against laser-induced fault injectionAlexandre Sarafianos, Mathieu Lisart, Olivier Gagliano, Valerie Serradeil, Cyril Roscian, Jean-Max Dutertre, Assia Tria. 149-154 [doi]
• A low cost reliable architecture for S-Boxes in AES processorsTing An, Lirida Alves de Barros Naviner, Philippe Matherat. 155-160 [doi]
• Variation-tolerant cache by two-layer error control codesMeilin Zhang, Paul Ampadu. 161-166 [doi]
• Implementing triple adjacent Error Correction in double error correction Orthogonal Latin Squares CodesPedro Reviriego, Shih-Fu Liu, Juan Antonio Maestro, S. Lee, Nur A. Touba, Rudrajit Datta. 167-171 [doi]
• Improved image accuracy in Hot Pixel degraded digital camerasGlenn H. Chapman, Rohit Thomas, Israel Koren, Zahava Koren. 172-177 [doi]
• Impact of mid-bond testing in 3D stacked ICsMottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen, Sudipta Bhawmik. 178-183 [doi]
• Unified 3D test architecture for variable test data bandwidth across pre-bond, partial stack, and post-bond testYu-Wei Lee, Nur A. Touba. 184-189 [doi]
• Analyzing circuit vulnerability to hardware Trojan insertion at the behavioral levelHassan Salmani, Mohammad Tehranipoor. 190-195 [doi]
• Secure Split-Test for preventing IC piracy by untrusted foundry and assemblyGustavo K. Contreras, Md. Tauhidur Rahman, Mohammad Tehranipoor. 196-203 [doi]
• Differential analysis of Round-Reduced AES faulty ciphertextsAmir-Pasha Mirbaha, Jean-Max Dutertre, Assia Tria. 204-211 [doi]
• Charge sharing aware NCL gates designMatheus T. Moreira, Bruno S. Oliveira, Fernando Gehm Moraes, Ney Laert Vilar Calazans. 212-217 [doi]
• Reliability analysis of combinational circuits with the influences of noise and single-event transientsKaikai Liu, Hao Cai, Ting An, Lirida A. B. Naviner, Jean-François Naviner, Hervé Petit. 218-223 [doi]
• Online TSV health monitoring and built-in self-repair to overcome agingCaleb Serafy, Ankur Srivastava. 224-229 [doi]
• Impact of PVT variation on delay test of resistive open and resistive bridge defectsShida Zhong, S. Saqib Khursheed, Bashir M. Al-Hashimi. 230-235 [doi]
• SmartInjector: Exploiting intelligent fault injection for SDC rate analysisJianli Li, Qingping Tan. 236-242 [doi]
• Built-in Self-Repair in a 3D die stack using programmable logicKundan Nepal, Xi Shen, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar. 243-248 [doi]
• Spare sharing network enhancement for scalable systemsSoroush Khaleghi, Wenjing Rao. 249-254 [doi]
• Automated integration of fault injection into the ASIC design flowAleksandar Simevski, Rolf Kraemer, Milos Krstic. 255-260 [doi]
• Modeling and analysis of repair and maintenance processes in Fault Tolerant SystemsJ.-Y. Hung, Noh-Jin Park, K. M. George, Nohpill Park. 261-265 [doi]
• Exploiting error control approaches for Hardware Trojans on Network-on-Chip linksQiaoyan Yu, Jonathan Frey. 266-271 [doi]
• Framework for dynamic estimation of power-supply noise and path delaySushmita Kadiyala Rao, Ryan Robucci, Chintan Patel. 272-277 [doi]
• A smart Trojan circuit and smart attack method in AES encryption circuitsMasayoshi Yoshimura, Amy Ogita, Toshinori Hosokawa. 278-283 [doi]
• On-chip error correction with unreliable decoders: Fundamental physical limitsNatesh Ganesh, Neal G. Anderson. 284-289 [doi]
• Reconfigurable distributed fault tolerant routing algorithm for on-chip networksManoj Kumar, Pankaj Kumar Srivastava, Vijay Laxmi, Manoj Singh Gaur, Seok-Bum Ko. 290-295 [doi]
• BIST for logic and local interconnect resources in a novel mesh of cluster FPGASaif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel. 296-301 [doi]
• Testing of switch blocks in TSV-reduced Three-Dimensional FPGAKouta Maebashi, Kazuteru Namba, Masato Kitakami. 302-307 [doi]