A low power architecture for online detection of execution errors in SMT processors

Rance Rodrigues, Sandip Kundu. A low power architecture for online detection of execution errors in SMT processors. In 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2013, New York City, NY, USA, October 2-4, 2013. pages 33-38, IEEE, 2013. [doi]

Abstract

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