Abstract is missing.
- Improving test pattern generation in presence of unknown values beyond restricted symbolic logicKarsten Scheibler, Dominik Erb, Bernd Becker. 1-6 [doi]
- Compact test set generation for test compression-based designsStephan Eggersglus. 1-6 [doi]
- Analog test: Why still "à la mode" after more than 25 years of research?Florence Azaïs. 1 [doi]
- NBTI and leakage aware sleep transistor design for reliable and energy efficient power gatingDaniele Rossi, Vasileios Tenentes, S. Saqib Khursheed, Bashir M. Al-Hashimi. 1-6 [doi]
- Protecting caches against multi-bit errors using embedded erasure codingAbbas BanaiyanMofrad, Mojtaba Ebrahimi, Fabian Oboril, Mehdi Baradaran Tahoori, Nikil D. Dutt. 1-6 [doi]
- High frequency jitter estimator for SoCsHerve Le Gall, Rshdee Alhakim, Miroslav Valka, Salvador Mir, Haralampos-G. D. Stratigopoulos, Emmanuel Simeu. 1-6 [doi]
- Robust amplitude measurement for RF BIST applicationsJae-woong Jeong, Jennifer Kitchen, Sule Ozev. 1-6 [doi]
- Microfluidic very large-scale integration for biochips: Technology, testing and fault-tolerant designIsmail Emre Araci, Paul Pop, Krishnendu Chakrabarty. 1-8 [doi]
- Cyber-physical systems: A security perspectiveCharalambos Konstantinou, Michail Maniatakos, Fareena Saqib, Shiyan Hu, Jim Plusquellic, Yier Jin. 1-8 [doi]
- On resistive open defect detection in DRAMs: The charge accumulation effectYiorgos Sfikas, Yiorgos Tsiatouhas, Mottaqiallah Taouil, Said Hamdioui. 1-6 [doi]
- Expanding the boundaries of test and diagnostics: Prognostics and Health Management (PHM) for complex systemsDouglas Goodman. 1 [doi]
- On test program compactionMarco Gaudesi, Matteo Sonza Reorda, Irith Pomeranz. 1-6 [doi]
- A branch-&-bound algorithm for TAM optimization in multi-Vdd SoCsFotios Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty. 1-2 [doi]
- An effective hybrid fault-tolerant architecture for pipelined coresI. Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard. 1-6 [doi]
- Branch guided functional test generation at the RTLVineeth V. Acharya, Sharad Bagri, Michael S. Hsiao. 1-6 [doi]
- A Bayesian model for system level reliability estimationAlessandro Vallero, Alessandro Savino, Sotiris Tselonis, Nikos Foutris, Manolis Kaliorakis, Gianfranco Politano, Dimitris Gizopoulos, Stefano Di Carlo. 1-2 [doi]
- Designing area-efficient controllers for multi-cycle transient fault tolerant systemsTsuyoshi Iwagaki, Yutaro Ishimori, Hideyuki Ichihara, Tomoo Inoue. 1-2 [doi]
- An ECC-based memory architecture with online self-repair capabilities for reliability enhancementGian Mayuga, Yuta Yamato, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato. 1-6 [doi]
- Reliability analysis for power MOSFET based on multi-physics simulationShuo Li, Hong Wang, Shiyuan Yang. 1-2 [doi]
- Identification of high power consuming areas with gate type and logic level informationKohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara. 1-6 [doi]
- Tackling the complexity of exact path delay fault grading for path intensive circuitsStelios N. Neophytou, Maria K. Michael. 1-2 [doi]
- A new technique for low-cost phase noise production testing from 1-bit signal acquisitionStephane David-Grignot, Florence Azaïs, Laurent Latorre, Francois Lefevre. 1-6 [doi]
- Improve the compression ratios for code-based test vector compressions by decomposingJishun Kuang, Liang Zhang, Zhiqiang You, Yingbo Zhou. 1-6 [doi]
- A practical approach for logic simplification based on fault acceptability for error tolerant applicationHideyuki Ichihara, Junpei Kamei, Tsuyoshi Iwagaki, Tomoo Inoue. 1-2 [doi]
- Advancements in diagnosis driven yield analysis (DDYA): A survey of state-of-the-art scan diagnosis and yield analysis technologiesYu Huang, Wu Yang, Wu-Tung Cheng. 1-10 [doi]
- Boundary cost optimization for Alternate TestGildas Leger. 1-6 [doi]
- Evaluating the self-testing property of AES' finite field inversion unitsFlavius Opritoiu, Mircea Vladutiu. 1-2 [doi]
- Symmetric transparent on-line BIST of word-organized memories with binary addersIoannis Voyiatzis. 1-2 [doi]
- LSI aging estimation using ring oscillatorsYukiya Miura, Tatsunori Ikeda. 1-2 [doi]
- Efficient diagnosis technique for aging defects on automotive semiconductor chipsJihun Jung, Muhammad Adil Ansari, Dooyoung Kim, Hyunbean Yi, Sungju Park. 1-2 [doi]
- Power-aware voltage tuning for STT-MRAM reliabilityElena I. Vatajelu, Rosa Rodríguez-Montañés, Stefano Di Carlo, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras. 1-6 [doi]
- New drain current model for nano-meter MOS transistors on-chip threshold voltage testJinbo Wan, Hans G. Kerkhoff. 1-6 [doi]
- Re-using BIST for circuit aging monitoringFarshad Firouzi, Fangming Ye, Arunkumar Vijayan, Abhishek Koneru, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori. 1-2 [doi]
- A soft-error tolerant TCAM using partial don't-care keysInfall Syafalni, Tsutomu Sasao, Xiaoqing Wen, Stefan Holst, Kohei Miyase. 1-2 [doi]
- A low capture power test generation method using capture safe test vectorsAtsushi Hirai, Yukari Yamauchi, Toshinori Hosokawa, Masayuki Arai. 1-2 [doi]
- Aging guardband reduction through selective flip-flop optimizationMohammad Saber Golanbari, Saman Kiamehr, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori. 1-6 [doi]
- Improving RO-PUF quality on FPGAs by incorporating design-dependent frequency biasesLinus Feiten, Tobias Martin, Matthias Sauer, Bernd Becker. 1-6 [doi]
- Variability-aware aging modeling for reliability analysis of an analog neural measurement systemNils Heidmann, Nico Hellwege, Steffen Paul, Dagmar Peters-Drolshagen. 1-6 [doi]
- Software-based repair for memories in tiny embedded systemsMario Schölzel, Patryk Skoncej. 1-2 [doi]
- A fault tolerant response analyzer with self-error-correction capabilityYuki Fukazawa, Hideyuki Ichihara, Tomoo Inoue. 1-2 [doi]
- Automatic generation of autonomous built-in observability structures for analog circuitsAnthony Coyette, Baris Esen, Ronny Vanhooren, Wim Dobbelaere, Georges G. E. Gielen. 1-6 [doi]
- Testing of Analog/Mixed Signal ICs: Past, present and futureBram Kruseman. 1 [doi]
- Software-based self-test techniques of computational modules in dual issue embedded processorsPaolo Bernardi, C. Bovi, Riccardo Cantoro, Sergio de Luca, Renato Meregalli, D. Piumatti, Ernesto Sánchez, Alessandro Sansonetti. 1-2 [doi]
- An FPGA-based ATE extension module for low-cost multi-GHz memory testDavid C. Keezer, Te-Hui Chen, Thomas Moon, D. T. Stonecypher, Abhijit Chatterjee, Hyun Woo Choi, Sungyeol Kim, Hosun Yoo. 1-6 [doi]
- Testing of digital microfluidic biochips with arbitrary layoutsTrung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, Krishnendu Chakrabarty. 1-2 [doi]
- Is adaptive testing the panacea for the future test problems?Zebo Peng. 1 [doi]
- Reliability-aware operation chaining in high level synthesisLiang Chen, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori. 1-6 [doi]
- Session-less based thermal-aware 3D-SIC test schedulingMarie-Lise Flottes, Joao Azevedo, Giorgio Di Natale, Bruno Rouzeyre. 1-2 [doi]
- Testing visionsHans-Joachim Wunderlich. 1 [doi]
- Diagnosis of power switches with power-distribution-network considerationVasileios Tenentes, Daniele Rossi, S. Saqib Khursheed, Bashir M. Al-Hashimi. 1-6 [doi]