Abstract is missing.
- Understanding customer returns from a test perspectiveNik Sumikawa, Dragoljub Gagi Drmanac, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir. 2-7 [doi]
- A distributed AXI-based platform for post-silicon validationMohammad Hossein Neishaburi, Zeljko Zilic. 8-13 [doi]
- Efficient trace data compression using statically selected dictionaryKanad Basu, Prabhat Mishra. 14-19 [doi]
- A built-in self-test scheme for the post-bond test of TSVs in 3D ICsYu-Jen Huang, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu. 20-25 [doi]
- Scan chain and power delivery network synthesis for pre-bond test of 3D ICsShreepad Panth, Sung Kyu Lim. 26-31 [doi]
- Exploiting rotational symmetries for improved stacked yields in W2W 3D-SICsEshan Singh. 32-37 [doi]
- Expedited response compaction for scan power reductionSamah Mohamed Saeed, Ozgur Sinanoglu. 40-45 [doi]
- Leakage power profiling and leakage power reduction using DFT hardwareRajamani Sethuram, Karim Arabi, Mohamed H. Abu-Rahma. 46-51 [doi]
- Levelized low cost delay test compaction considering IR-drop induced power supply noiseZhongwei Jiang, Zheng Wang, Jing Wang 0006, D. M. H. Walker. 52-57 [doi]
- Automatic test stimulus generation for accurate diagnosis of RF systems using transient response signaturesAritra Banerjee, Shreyas Sen, Shyam Kumar Devarakond, Abhijit Chatterjee. 58-63 [doi]
- Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficientsSuraj Sindia, Vishwani D. Agrawal, Virendra Singh. 64-69 [doi]
- A diagnosis testbench of analog IP cores against on-chip environmental disturbancesTakushi Hashida, Yuuki Araga, Makoto Nagata. 70-75 [doi]
- Case Study: Efficient SDD test generation for very large integrated circuitsKe Peng, Fang Bao, Geoff Shofner, LeRoy Winemberg, Mohammad Tehranipoor. 78-83 [doi]
- Static test compaction for delay fault test sets consisting of broadside and skewed-load testsIrith Pomeranz. 84-89 [doi]
- Efficient and product-representative timing model validationEun-jung Jang, Anne E. Gattiker, Sani R. Nassif, Jacob A. Abraham. 90-95 [doi]
- Special session: Multifaceted approaches for field reliabilityYasuo Sato. 96 [doi]
- Advanced methods for leveraging new test standardsMike Laisne. 97 [doi]
- Special session 4A: New topics parametric yield and reliability of 3D integrated circuits: New challenges and solutionsSiddharth Garg, Diana Marculescu. 99 [doi]
- Security-aware SoC test access mechanismsKurt Rosenfeld, Ramesh Karri. 100-104 [doi]
- Design and analysis of ring oscillator based Design-for-Trust techniqueJeyavijayan Rajendran, Vinayaka Jyothi, Ozgur Sinanoglu, Ramesh Karri. 105-110 [doi]
- The buck stops with wafer test: Dream or reality?Suriyaprakash Natarajan, Arani Sinha. 111 [doi]
- Apprentice - VTS edition: Season 4Kee Sup Kim, Rob Roy. 113 [doi]
- Special session 5B: Panel How much toggle activity should we be testing with?Xiaoqing Wen, Mohammad Tehranipoor, Rohit Kapur, Anand Bhat, Amitava Majumdar, LeRoy Winemberg. 114 [doi]
- A Novel mechanism for speed characterization during delay testAmitava Majumdar, Arani Sinha, Nehal Patel, Ramamurthy Setty, Yan Dong, Shu-Hsuan Chou. 116-121 [doi]
- An efficient method to screen resistive opens under presence of process variationSeongmoon Wang. 122-127 [doi]
- On clustering of undetectable transition faults in standard-scan circuitsIrith Pomeranz. 128-133 [doi]
- Designing a fast and adaptive error correction scheme for increasing the lifetime of phase change memoriesRudrajit Datta, Nur A. Touba. 134-139 [doi]
- Programmable extended SEC-DED codes for memory errorsValentin Gherman, Samuel Evain, Fabrice Auzanneau, Yannick Bonhomme. 140-145 [doi]
- Training-based forming process for RRAM yield improvementHsiu-Chuan Shih, Ching-Yi Chen, Cheng-Wen Wu, Chih-He Lin, Shyh-Shyuan Sheu. 146-151 [doi]
- The bang for the buck with resiliency: Yield or field?Arani Sinha, Suriyaprakash Natarajan. 152 [doi]
- Modified flip-flop architecture to reduce hold buffers and peak power during scan shift operationPrakash Narayanan, Rajesh Mittal, Sumanth Poddutur, Vivek Singhal, Puneet Sabbarwal. 154-159 [doi]
- Power-safe test application using an effective gating approach considering current limitsWei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty. 160-165 [doi]
- Power-aware test generation with guaranteed launch safety for at-speed scan testingXiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor. 166-171 [doi]
- SLIDER: A fast and accurate defect simulation frameworkWing Chiu Tam, Ronald D. Blanton. 172-177 [doi]
- An industrial case study of analog fault modelingEnder Yilmaz, Anne Meixner, Sule Ozev. 178-183 [doi]
- A new methodology for realistic open defect detection probability evaluation under process variationsJesus Moreno, Víctor H. Champac, Michel Renovell. 184-189 [doi]
- Impact of the application activity on intermittent faults in embedded systemsJulien Guilhemsang, Olivier Héron, Nicolas Ventroux, Olivier Goncalves, Alain Giulieri. 191-196 [doi]
- An analytical method for estimating SET propagationSreenivas Gangadhar, Spyros Tragoudas. 197-202 [doi]
- Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensorsC. V. Martins, Jorge Semião, Julio César Vázquez, Víctor H. Champac, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. 203-208 [doi]
- Coverage closure in SoC verification: Are we chasing a mirage?Shobha Vasudevan. 211 [doi]
- A scan cell architecture for inter-clock at-speed delay testingKyoung Youn Cho, Rajagopalan Srinivasan. 213-218 [doi]
- Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chipsAmit Sanghani, Bo Yang, Karthikeyan Natarajan, Chunsheng Liu. 219-224 [doi]
- Harmony Widget for X-free scan testingDilip K. Bhavsar. 225-228 [doi]
- Localization of damaged resources in NoC based shared-memory MP2SOC, using a Distributed Cooperative Configuration InfrastructureZhen Zhang, Dimitri Refauvelet, Alain Greiner, Mounir Benabdenbi, François Pêcheux. 229-234 [doi]
- Exponent monitoring for low-cost concurrent error detection in FPU control logicMichail Maniatakos, Yiorgos Makris, Prabhakar Kudva, Bruce M. Fleischer. 235-240 [doi]
- Enhancing online error detection through area-efficient multi-site implicationsNuno Alves, Yiwen Shi, Jennifer Dworak, R. Iris Bahar, Kundan Nepal. 241-246 [doi]
- Dynamic scan clock control for test time reduction maintaining peak power limitPriyadharshini Shanmugasundaram, Vishwani D. Agrawal. 248-253 [doi]
- Structural tests of slave clock gating in low-power flip-flopBaosheng Wang, Jayalakshmi Rajaraman, Kanwaldeep Sobti, Derrick Losli, Jeff Rearick. 254-259 [doi]
- Revival of partial scan: Test cube analysis driven conversion of flip-flopsNader Alawadhi, Ozgur Sinanoglu. 260-265 [doi]
- Memory-based embedded digital ATEDongsoo Lee, Sang Phill Park, Ashish Goel, Kaushik Roy. 266-271 [doi]
- A unified test architecture for on-line and off-line delay fault detectionsSongwei Pei, Huawei Li, Xiaowei Li. 272-277 [doi]
- Design for Bit Error Rate estimation of high speed serial linksUjjwal Guin, Chen-Huan Chiang. 278-283 [doi]
- An efficient test data reduction technique through dynamic pattern mixing across multiple fault modelsS. Alampally, R. T. Venkatesh, P. Shanmugasundaram, Rubin A. Parekhji, V. D. Agrawal. 285-290 [doi]
- Low Coverage Analysis using dynamic un-testability debug in ATPGKameshwar Chandrasekar, Surendra Bommu, Sanjay Sengupta. 291-296 [doi]
- Prediction of compression bound and optimization of compression architecture for linear decompression-based schemesJia Li, Yu Huang, Dong Xiang. 297-302 [doi]
- Multi Domain Test: Novel test strategy to reduce the Cost of TestYasuhiro Takahashi, Akinori Maeda. 303-308 [doi]
- Low-cost diagnostic pattern generation and evaluation procedures for noise-related failuresJunxia Ma, Nisar Ahmed, Mohammad Tehranipoor. 309-314 [doi]
- Sigma-delta modulation based wafer-level testing for TFT-LCD source driver ICsW.-A. Lin, C. C. Lee, J.-L. Huang. 315-320 [doi]
- Practical signal processing at mixed signal test venues - Trend removal, noise reduction, wideband signal capturing -Hideo Okawara. 322 [doi]
- Special session: Hot topic: Smart siliconLeRoy Winemberg, Mohammad Tehranipoor. 323 [doi]
- Invited paper: Yin and Yang of embedded sensors for post-scaling-eraAnne Gattiker. 324-327 [doi]
- Special session: Hot topic design and test of 3D and emerging memoriesCheng-Wen Wu. 328 [doi]