A scan cell architecture for inter-clock at-speed delay testing - researchr publication

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Kyoung Youn Cho, Rajagopalan Srinivasan. A scan cell architecture for inter-clock at-speed delay testing. In 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA. pages 213-218, IEEE Computer Society, 2011. [doi]

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