Prakash Narayanan, Rajesh Mittal, Sumanth Poddutur, Vivek Singhal, Puneet Sabbarwal. Modified flip-flop architecture to reduce hold buffers and peak power during scan shift operation. In 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA. pages 154-159, IEEE Computer Society, 2011. [doi]
Abstract is missing.