Table of Contents

• Murphy was an optimist: Embracing asymmetry in electronicsKerry Bernstein. [doi]
• Concolic testing of SystemC designsBin Lin, Kai Cong, Zhenkun Yang, Zhi-gang Liao, Tao Zhan, Christopher Havlicek, Fei Xie. 1-7 [doi]
• A droop measurement built-in self-test circuit for digital low-dropout regulatorsAydin Dirican, Cagatay Ozmen, Martin Margala. 8-13 [doi]
• Test set identification for improved delay defect coverage in the presence of statistical delaysPavan Kumar Javvaji, Basim Shanyour, Spyros Tragoudas. 14-19 [doi]
• Power-aware testing in the Era of IoTPatrick Girard. 17-20 [doi]
• Augmenting ESD and EOS physical analysis with per pin ESD and leakage DFTHoraira Abu, Salem Abdennadher, Benoit Provost, Harry Muljono. 20-24 [doi]
• Hybrid-comp: A criticality-aware compressed last-level cacheAmin Jadidi, Mohammad Arjomand, Mahmut T. Kandemir, Chita R. Das. 25-30 [doi]
• Energy-optimal dynamic voltage scaling in multicore platforms with reconfigurable power distribution networkJuyeon Kim, Taewhan Kim. 31-36 [doi]
• Optimizing energy in a DRAM based hybrid cacheJiacong He, Joseph Callenes-Sloan. 37-42 [doi]
• Program acceleration using nearest distance associative searchMohsen Imani, Daniel Peroni, Tajana Rosing. 43-48 [doi]
• Synthesis of normally-off boolean circuits: An evolutionary optimization approach utilizing spintronic devicesArman Roohi, Ramtin Zand, Ronald F. DeMara. 49-54 [doi]
• LUPIS: Latch-up based ultra efficient processing in-memory systemJoonseop Sim, Mohsen Imani, Woojin Choi, Yeseong Kim, Tajana Rosing. 55-60 [doi]
• Energy efficient neuromorphic processing using spintronic memristive device with dedicated synaptic and neuron terminologyZoha Pajouhi. 61-68 [doi]
• A bi-memristor synapse with spike-timing-dependent plasticity for on-chip learning in memristive neuromorphic systemsSagarvarma Sayyaparaju, Sherif Amer, Garrett S. Rose. 69-74 [doi]
• Recognition of regular layout structuresYu-Cheng Chiang, Shr-Cheng Tsai, Rung-Bin Lin. 75-81 [doi]
• A simplified methodology for complex analog module layout generationPradeep Kumar Chawda. 82-87 [doi]
• Process variation aware D-Flip-Flop design using regression analysisShinichi Nishizawa, Hidetoshi Onodera. 88-93 [doi]
• Clock buffer and flip-flop co-optimization for reducing peak current noiseJoohan Kim, Taewhan Kim. 94-99 [doi]
• Parasitic-aware gm/ID-based many-objective analog/RF circuit sizingTuotian Liao, Lihong Zhang. 100-105 [doi]
• A loop structure optimization targeting high-level synthesis of fast number theoretic transformKazushi Kawamura, Masao Yanagisawa, Nozomu Togawa. 106-111 [doi]
• A 4-PAM interconnect in network-on-chip for high-throughput and latency-sensitive applicationsAhmad Mansour, Ahmed El-Naggar, Bassma Al-Abassy, Mostafa Khamis, Ahmed Shalaby. 112-118 [doi]
• Comparative study and prediction modeling of photonic ring Network on Chip architecturesSara Karimi, Jelena Trajkovic. 119-126 [doi]
• Power and performance aware memory-controller voting mechanismMilena Vratonjic, Harmander Singh, Gautam Kumar, Roumi Mohamed, Ashish Bajaj, Ken Gainey. 127-130 [doi]
• PDA-HyPAR: Path-diversity-aware hybrid planar adaptive routing algorithm for 3D NoCsJindun Dai, Renjie Li, Xin Jiang, Takahiro Watanabe. 131-137 [doi]
• Network on interconnect fabricBoris Vaisband, Adeel A. Bajwa, Subramanian S. Iyer. 138-143 [doi]
• Efficient K nearest neighbor algorithm implementations for throughput-oriented architecturesJihyun Ryoo, Meena Arunachalam, Rahul Khanna, Mahmut T. Kandemir. 144-150 [doi]
• Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAMJheng-Yi Chen, Ming-Yu Chang, Shi-Hao Chen, Jia-Wei Lee, Meng-Hsueh Chiang. 151-155 [doi]
• Measuring the effectiveness of ISO26262 compliant self test libraryFrederico Pratas, Thomas Dedes, Andrew Webber, Majid Bemanian, Itai Yarom. 156-161 [doi]
• An online framework for diagnosis of multiple defects in scan chainsSarmad Tanwir, Michael S. Hsiao, Loganathan Lingappan. 162-168 [doi]
• Routing at compile timeChun-Xun Lin, Tsung-Wei Huang, Martin D. F. Wong. 169-175 [doi]
• Uncertainty aware mapping of embedded systems for reliability, performance, and energyWenkai Guan, Milad Ghorbani Moghaddam, Cristinel Ababei. 176-183 [doi]
• On the write energy of non-volatile resistive crossbar arrays with selectorsAlbert Ciprut, Eby G. Friedman. 184-188 [doi]
• A modified method of logical effort for FinFET circuits considering impact of fin-extension effectsArchana Pandey, Pitul Garg, Shobhit Tyagi, Rajeev Ranjan, Anand Bulusu. 189-195 [doi]
• Generic system-level modeling and optimization for beyond CMOS device applicationsVictor Huang, Chenyun Pan, Azad Naeemi. 196-200 [doi]
• Terahertz travelling wave amplifier design using Ballistic Deflection TransistorHuan Wang, Jean-François Millithaler, Ronald W. Knepper, Martin Margala. 201-206 [doi]
• Reliable memory PUF design for low-power applicationsMohammad Saber Golanbari, Saman Kiamehr, Rajendra Bishnoi, Mehdi Baradaran Tahoori. 207-213 [doi]
• An ESD transient clamp with 494 pA leakage current in GP 65 nm CMOS technologyMahdi Elghazali, Manoj Sachdev, Ajoy Opal. 214-220 [doi]
• Enhancing circuit operation using analog floating gatesUjas Patel, Sai Nimmalapudi, Harvey Stiegler, Andrew Marshall, Keith Jarreau. 221-226 [doi]
• An automated flow for design validation of switched mode power supplyPradeep Kumar Chawda, Shrikrishna Srinivasan. 227-231 [doi]
• Dynamic NoC platform for varied application needsSidhartha Sankar Rout, Hemanta Kumar Mondal, Rohan Juneja, Sri Harsha Gade, Sujay Deb. 232-237 [doi]
• A technique to aggregate classes of analog fault diagnostic data based on association rule miningRuslan Dautov, Sergey G. Mosin. 238-243 [doi]
• Extracting hardware assertions including word-level relations over multiple clock cyclesMami Miyamoto, Kiyoharu Hamaguchi. 244-250 [doi]
• A study on NBTI-induced delay degradation considering stress frequency dependenceZuitoku Shin, Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato. 251-256 [doi]
• Verification methodology to guarantee low routing resistance to well tapsMohammed Fakhruddin, Kuok-Khian Lo, James Karp, Michael J. Hart, Min-Hsing P. Chen. 257-261 [doi]
• Ultra-low swing CMOS transceiver for 2.5-D integrated systemsPrzemyslaw Mroszczyk, Vasilis F. Pavlidis. 262-267 [doi]
• Back-bias generator for post-fabrication threshold voltage tuning applications in 22nm FD-SOI processArif Siddiqi, Navneet Jain, Mahbub Rashed. 268-273 [doi]
• Logic-based row redundancy technique designed in 7nm FinFET technology for embedded SRAMsVivek Nautiyal, Nishant Nukala, Fakhruddin ali Bohra, Sagar Dwivedi, Jitendra Dasani, Satinderjit Singh, Gaurav Singla, Martin Kinkade. 274-279 [doi]
• A 125mV 2ns-access-time 16Kb SRAM design based on a 6T hybrid TFET-FinFET cellHassan Afzali-Kusha, Alireza Shafaei, Massoud Pedram. 280-285 [doi]
• New AC resistance calculation of printed spiral coils for wireless power transferGaorong Qian, Yuhua Cheng, Guoxiong Chen, Gaofeng Wang. 286-289 [doi]
• An automated design flow for synthesis of optimal multi-layer multi-shape PCB coils for inductive sensing applicationsPradeep Kumar Chawda. 290-295 [doi]
• When "things" get older: Exploring circuit aging in IoT applicationsXinfei Guo, Vaibhav Verma, Patricia Gonzalez-Guerrero, Mircea R. Stan. 296-301 [doi]
• A deep learning based approach for analog hardware implementation of delayed feedback reservoir computing systemJialing Li, Kangjun Bai, Lingjia Liu, Yang Yi 0002. 308-313 [doi]
• An area and energy efficient design of domain-wall memory-based deep convolutional neural networks using stochastic computingXiaolong Ma, Yipeng Zhang, Geng Yuan, Ao Ren, Zhe Li 0001, Jie Han, Jingtong Hu, Yanzhi Wang. 314-321 [doi]
• A path to energy-efficient spiking delayed feedback reservoir computing system for brain-inspired neuromorphic processorsKangjun Bai, Yang Yi Bradley. 322-328 [doi]
• Low power latch based design with smart retimingKamlesh Singh, Hailong Jiao, Jos Huisken, Hamed Fatemi, José Pineda de Gyvez. 329-334 [doi]
• Parallel implementation of finite state machines for reducing the latency of stochastic computingCong Ma, David J. Lilja. 335-340 [doi]
• A post-silicon hold time closure technique using data-path tunable-buffers for variation-tolerance in sub-threshold designsDivya Akella Kamakshi, Xinfei Guo, Harsh N. Patel, Mircea R. Stan, Benton H. Calhoun. 341-346 [doi]
• A low-power configurable adder for approximate applicationsTongxin Yang, Tomoaki Ukezono, Toshinori Sato. 347-352 [doi]
• Mathematical derivation, circuits design and clinical experiments of measuring blood flow volume (BFV) at arteriovenous fistula (AVF) of hemodialysis (HD) patients using a newly-developed photoplethysmography (PPG) sensorPaul C.-P. Paul, Pei-Yu Chiang, Der-Cherng Tarng, Chih-Yu Yang. 353-356 [doi]
• A wireless multifunctional monitoring system of tower body running state based on MEMS acceleration sensorLinxi Dong, Haonan Wang, Gaofeng Wang, Weimin Qiu. 357-363 [doi]
• Power management factors and techniques for IoT design devicesAnupriya Prasad, Pradeep Chawda. 364-369 [doi]
• Hierarchical dynamic goal management for IoT systemsAxel Jantsch, Arman Anzanpour, Hedyeh A. Kholerdi, Iman Azimi, Lydia C. Siafara, Amir M. Rahmani, Nima Taherinejad, Pasi Liljeberg, Nikil D. Dutt. 370-375 [doi]
• Quantized neural networks with new stochastic multipliersBingzhe Li, M. Hassan Najafi, Bo Yuan, David J. Lilja. 376-382 [doi]
• High performance training of deep neural networks using pipelined hardware acceleration and distributed memoryRaghav Mehta, Yuyang Huang, Mingxi Cheng, Shrey Bagga, Nishant Mathur, Ji Li, Jeffrey Draper, Shahin Nazarian. 383-388 [doi]
• Deep neural network acceleration framework under hardware uncertaintyMohsen Imani, Pushen Wang, Tajana Rosing. 389-394 [doi]
• A hardware-friendly algorithm for scalable training and deployment of dimensionality reduction models on FPGAMahdi Nazemi, Amir Erfan Eshratifar, Massoud Pedram. 395-400 [doi]
• Securing FPGA-based obsolete component replacement for legacy systemsZhiming Zhang, Laurent Njilla, Charles A. Kamhoua, Kevin A. Kwiat, Qiaoyan Yu. 401-406 [doi]
• High-level synthesis of key based obfuscated RTL datapathsSheikh Ariful Islam, Srinivas Katkoori. 407-412 [doi]
• Double error cellular automata-based error correction with skip-mode compact syndrome coding for resilient PUF designAnthony Mattar El Raachini, Hussein Alawieh, Adam Issa, Zainab Swaidan, Rouwaida Kanj, Ali Chehab, Mazen A. R. Saghir. 413-418 [doi]
• Design and evaluation of physical unclonable function for inorganic printed electronicsAhmet Turan Erozan, Mohammad Saber Golanbari, Rajendra Bishnoi, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori. 419-424 [doi]
• Near-future traffic evaluation based navigation for automated driving vehicles considering traffic uncertaintiesKuen-Wey Lin, Masanori Hashimoto, Yih-Lang Li. 425-431 [doi]
• Low cost and power CNN/deep learning solution for automated drivingMihir Mody, Kumar Desappan, Pramod Swami, Manu Mathew, Soyeb Nagori. 432-436 [doi]
• Resource constrained cellular neural networks for real-time obstacle detection using FPGAsXiaowei Xu, Tianchen Wang, Qing Lu, Yiyu Shi. 437-440 [doi]