Archana Pandey, Pitul Garg, Shobhit Tyagi, Rajeev Ranjan, Anand Bulusu. A modified method of logical effort for FinFET circuits considering impact of fin-extension effects. In 19th International Symposium on Quality Electronic Design, ISQED 2018, Santa Clara, CA, USA, March 13-14, 2018. pages 189-195, IEEE, 2018. [doi]
Abstract is missing.