A hardware-friendly algorithm for scalable training and deployment of dimensionality reduction models on FPGA

Mahdi Nazemi, Amir Erfan Eshratifar, Massoud Pedram. A hardware-friendly algorithm for scalable training and deployment of dimensionality reduction models on FPGA. In 19th International Symposium on Quality Electronic Design, ISQED 2018, Santa Clara, CA, USA, March 13-14, 2018. pages 395-400, IEEE, 2018. [doi]

Abstract

Abstract is missing.