Mahdi Nazemi, Amir Erfan Eshratifar, Massoud Pedram. A hardware-friendly algorithm for scalable training and deployment of dimensionality reduction models on FPGA. In 19th International Symposium on Quality Electronic Design, ISQED 2018, Santa Clara, CA, USA, March 13-14, 2018. pages 395-400, IEEE, 2018. [doi]
@inproceedings{NazemiEP18,
title = {A hardware-friendly algorithm for scalable training and deployment of dimensionality reduction models on FPGA},
author = {Mahdi Nazemi and Amir Erfan Eshratifar and Massoud Pedram},
year = {2018},
doi = {10.1109/ISQED.2018.8357319},
url = {https://doi.org/10.1109/ISQED.2018.8357319},
researchr = {https://researchr.org/publication/NazemiEP18},
cites = {0},
citedby = {0},
pages = {395-400},
booktitle = {19th International Symposium on Quality Electronic Design, ISQED 2018, Santa Clara, CA, USA, March 13-14, 2018},
publisher = {IEEE},
isbn = {978-1-5386-1214-9},
}