Table of Contents

• Reduced code linearity testing of pipeline adcs in the presence of noiseAsma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Herve Naudet, Gerard Bret. 1-6 [doi]
• An iterative diagnosis approach for ECC-based memory repairPanagiota Papavramidou, Michael Nicolaidis. 1-6 [doi]
• Low-cost multi-channel testing of periodic signals using monobit receivers and incoherent subsamplingThomas Moon, Hyun Woo Choi, Abhijit Chatterjee. 1-6 [doi]
• A study on the effectiveness of Trojan detection techniques using a red team blue team approachX. Zhang, Kan Xiao, Mohammad Tehranipoor, Jeyavijayan Rajendran, Ramesh Karri. 1-3 [doi]
• Defect-oriented non-intrusive RF test using on-chip temperature sensorsLouay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Josep Altet. 1-6 [doi]
• Special session 9B: Embedded tutorial embedded DfT instrumentation: Design, access, retargeting and case studiesErik Larsson. 1-2 [doi]
• Scalable dynamic technique for accurately predicting power-supply noise and path delaySushmita Kadiyala Rao, Ryan Robucci, Chintan Patel. 1-6 [doi]
• Allocation of RAM built-in self-repair circuits for SOC dies of 3D ICsChih-Sheng Hou, Jin-Fu Li. 1-6 [doi]
• On the investigation of built-in tuning of RF receivers using on-chip polyphase filtersHaddad Fayrouz, Wenceslas Rahajandraibe, Hassen Aziza, K. Castellani-Coulié, Jean Michel Portal. 1-6 [doi]
• Experiences in side channel and testing based Hardware Trojan detectionDavid Hély, Julien Martin, Gerson Dario Piraquive Triana, Simon Piroux Mounier, Elie Riviere, Thibault Sahuc, Jeremy Savonet, Laura Soundararadjou. 1-4 [doi]
• RSAK: Random stream attack for phase change memory in video applicationsYuntan Fang, Huawei Li, Xiaowei Li 0001. 1-6 [doi]
• Testing of a low-VMIN data-aware dynamic-supply 8T SRAMChen-Wei Lin, Chin-Yuan Huang, Mango Chia-Tso Chao. 1-6 [doi]
• Testing retention flip-flops in power-gated designsHao-Wen Hsu, Shih-Hua Kuo, Wen-Hsiang Chang, Shi-Hao Chen, Ming-Tung Chang, Mango Chia-Tso Chao. 1-6 [doi]
• 3D-IC interconnect test, diagnosis, and repairChun-Chuan Chi, Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin. 1-6 [doi]
• Innovative practices session 2C: Memory testCharutosh Dixit, Ramesh C. Tekumalla, Sreejit Chakravarty, Charutosh Dixit, Manuel d'Abreu, Zhuoyu Bao, Concetta Riccobene. 1 [doi]
• Measurement of envelope/phase path delay skew and envelope path bandwidth in polar transmittersJae-woong Jeong, Sule Ozev, Shreyas Sen, T. M. Mak. 1-6 [doi]
• Test-cost optimization and test-flow selection for 3D-stacked ICsMukesh Agrawal, Krishnendu Chakrabarty. 1-6 [doi]
• SOC test compression scheme using sequential linear decompressors with retained free variablesSreenivaas S. Muthyala, Nur A. Touba. 1-6 [doi]
• Distributed dynamic partitioning based diagnosis of scan chainYu Huang, Xiaoxin Fan, Huaxing Tang, Manish Sharma, Wu-Tung Cheng, Brady Benware, Sudhakar M. Reddy. 1-6 [doi]
• Special session 12C: Town-hall meeting "young professionals in test"Alodeep Sanyal, Yervant Zorian. 1 [doi]
• Innovative practices session 11C: ResilienceChen-Yong Cher, Mohan J. Kumar. 1 [doi]
• Special session 11B: Hot topic on-chip clocking - Industrial trendsAnshuman Chandra. 1 [doi]
• A built-in scheme for testing and repairing voltage regulators of low-power sramsLeonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine. 1-6 [doi]
• Experiments and analysis to characterize logic state retention limitations in 28nm process nodeSachin Dileep Dasnurkar, Animesh Datta, Mohamed H. Abu-Rahma, Hieu Nguyen, Martin Villafana, Hadi Rasouli, Sean Tamjidi, Ming Cai, Samit Sengupta, P. R. Chidambaram, Raghavan Thirumala, Nikhil Kulkarni, Prasanna Seeram, Prasad Bhadri, Prayag Patel, Sei Seung Yoon, Esin Terzioglu. 1-6 [doi]
• Special session 8B: Embedded tutorial challenges in SSDManuel d'Abreu, Amitava Mazumdar. 1 [doi]
• Innovative practices session 5C: Cloud atlas - Unreliability through massive connectivityHelia Naeimi, Suriya Natarajan, Kushagra Vaid, Prabhakar Kudva, Mahesh Natu. 1 [doi]
• New topic session 7B: Challenges and directions for ultra-low voltage VLSI circuits and systems: CMOS and beyondBozena Kaminska, Bernard Courtois, Bernard Courtois, Massimo Alioto. 1 [doi]
• Special session 12A: Hot topic counterfeit IC identification: How can test help?Ilia Polian, Mohammad Tehranipoor. 1 [doi]
• Hot topic session 4A: Reliability analysis of complex digital systemsAdrian Evans, Michael Nicolaidis, Rob Aitken, Burcin Aktan, Olivier Lauzeral. 1 [doi]
• An IDDQ BIST approach to characterize phase-locked loop parametersSamed Maltabas, Osman Kubilay Ekekon, Kemal Kulovic, Anne Meixner, Martin Margala. 1-6 [doi]
• Towards a cost-effective hardware trojan detection methodologyRaymond Paseman, Alex Orailoglu. 1-3 [doi]
• An effective solution for building memory BIST infrastructure based on fault periodicityGurgen Harutyunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian. 1-6 [doi]
• Special session 3B: E.J. McCluskey Doctoral Thesis Award semi-final - PostersMichele Portolan, Michail Maniatakos. 1 [doi]
• Innovative practices session 10C: Delay testP. Pant, M. Amodeo, S. Vora, J. Colburn. 1 [doi]
• RAVAGE: Post-silicon validation of mixed signal systems using genetic stimulus evolution and model tuningBarry John Muldrey, Sabyasachi Deyati, Michael Giardino, Abhijit Chatterjee. 1-6 [doi]
• Investigation of gate oxide short in FinFETs and the test methods for FinFET SRAMsChen-Wei Lin, Mango Chia-Tso Chao, Chih-Chieh Hsu. 1-6 [doi]
• On-chip circuit for measuring multi-GHz clock signal waveformsK. A. Jenkins, Phillip Restle, P. Z. Wang, D. Hogenmiller, D. Boerstler, Thomas J. Bucelot. 1-4 [doi]
• Power supply noise control in pseudo functional testTengteng Zhang, Duncan M. Hank Walker. 1-6 [doi]
• Identification of critical variables using an FPGA-based fault injection frameworkAndreas Riefert, Jörg Müller 0004, Matthias Sauer, Wolfram Burgard, Bernd Becker. 1-6 [doi]
• Special session 4B: Elevator talksJennifer Dworak, Ronald Shawn Blanton, Masahiro Fujita, Kazumi Hatayama, Naghmeh Karimi, Michail Maniatakos, Antonis M. Paschalis, Adit D. Singh, Tian Xia. 1 [doi]
• A programmable BIST design for PLL static phase offset estimation and clock duty cycle detectionSen-Wen Hsiao, Nicholas Tzou, Abhijit Chatterjee. 1-6 [doi]
• Special session 8A: E.J. McCluskey doctoral thesis award semi-final - presentationsMichele Portolan, Michail Maniatakos. 1 [doi]
• A hybrid ECC and redundancy technique for reducing refresh power of DRAMsYun-Chao You, Chih-Sheng Hou, Li-Jung Chang, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu. 1-6 [doi]
• Innovative practices session 9C: Yield improvement: Challenges and directionsB. Seshadri, B. Cory, S. Mitra, B. Seshadri. 1 [doi]
• Combining checkpointing and scrubbing in FPGA-based real-time systemsAitzan Sari, Mihalis Psarakis, Dimitris Gizopoulos. 1-6 [doi]
• A multi-parameter functional side-channel analysis method for hardware trust verificationChristopher Bell, Matthew Lewandowski, Srinivas Katkoori. 1-4 [doi]
• Selection of tests for outlier detectionHarm C. M. Bossers, Johann L. Hurink, Gerard J. M. Smit. 1-6 [doi]
• Chip-level modeling and analysis of electrical masking of soft errorsSaman Kiamehr, Mojtaba Ebrahimi, Farshad Firouzi, Mehdi Baradaran Tahoori. 1-6 [doi]
• Innovative practices session 7C: Self-calibration & trimmingChen-Yong Cher, Yiorgos Makris, C. Thibeault, Alan J. Drake. 1 [doi]
• A framework for low overhead hardware based runtime control flow error detection and recoveryAmeya Chaudhari, Junyoung Park, Jacob A. Abraham. 1-6 [doi]
• Post-DfT-insertion retiming for delay recovery on inter-die paths in 3D ICsBrandon Noia, Krishnendu Chakrabarty. 1-6 [doi]
• Enhanced algorithm of combining trace and scan signals in post-silicon validationKihyuk Han, Joon-Sung Yang, Jacob A. Abraham. 1-6 [doi]
• Innovative practices session 1C: Post-silicon validationNagib Hakim, Charles Meissner. 1-2 [doi]
• Improving test generation by use of majority gatesPeter Wohl, John A. Waicukauski. 1-6 [doi]
• Testing of flow-based microfluidic biochipsKai Hu, Tsung-Yi Ho, Krishnendu Chakrabarty. 1-6 [doi]
• Novel estimation method of EVM with channel correction for linear impairments in multi-standard RF transceiversKoji Asami, Takashi Shimura, Toshiaki Kurihara. 1-6 [doi]
• Extending pre-silicon delay models for post-silicon tasks: Validation, diagnosis, delay testing, and speed binningPrasanjeet Das, Sandeep K. Gupta. 1-6 [doi]
• Trading off area, yield and performance via hybrid redundancy in multi-core architecturesYue Gao, Yang Zhang, Da Cheng, Melvin A. Breuer. 1-6 [doi]
• A multi-faceted approach to FPGA-based Trojan circuit detectionMichael Patterson, Aaron Mills, Ryan Scheel, Julie Tillman, Evan Dye, Joseph Zambreno. 1-4 [doi]
• Innovative practices session 6C: Latest practices in test compressionJ. Colburn, K.-Y. Chung, Haluk Konuk, Y. Dong. 1 [doi]
• Innovative practices session 3C: Harnessing the challenges of testability and debug of high speed I/OsSaghir A. Shaikh. 1 [doi]
• Contactless test access mechanism for TSV based 3D ICsRashid Rashidzadeh. 1-6 [doi]
• Finding best voltage and frequency to shorten power-constrained test timePraveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal. 1-6 [doi]
• Special session 12B: Panel post-silicon validation & test in huge variance eraTakahiro J. Yamaguchi, Jacob A. Abraham, Gordon W. Roberts, Suriyaprakash Natarajan, Dennis J. Ciplickas. 1 [doi]
• Path selection based on static timing analysis considering input necessary assignmentsBo Yao, Arani Sinha, Irith Pomeranz. 1-6 [doi]
• Special session 4C: Hot topic 3D-IC design and testJin-Fu Li, Cheng-Wen Wu, Cheng-Wen Wu, Masahiro Aoyagi, Meng-Fan Marvin Chang, Ding-Ming Kwai. 1 [doi]
• Tracing the best test mix through multi-variate quality trackingBaris Arslan, Alex Orailoglu. 1-6 [doi]
• New topic session 2B: Why (Re-)Designing Biology is ∗Slightly∗ more challenging than designing electronicsBozena Kaminska, Bernard Courtois, Bozena Kaminska, Soha Hassoun. 1 [doi]