Testing retention flip-flops in power-gated designs

Hao-Wen Hsu, Shih-Hua Kuo, Wen-Hsiang Chang, Shi-Hao Chen, Ming-Tung Chang, Mango Chia-Tso Chao. Testing retention flip-flops in power-gated designs. In 31st IEEE VLSI Test Symposium, VTS 2013, Berkeley, CA, USA, April 29 - May 2, 2013. pages 1-6, IEEE Computer Society, 2013. [doi]

Abstract

Abstract is missing.