Abstract is missing.
- Linearity test of high-speed high-performance ADCs using a self-testable on-chip generatorAntonio J. Ginés, Eduardo J. Peralías, Gildas Leger, Adoración Rueda, Guillaume Renaud, Manuel J. Barragan, Salvador Mir. 1-6 [doi]
- Practices in High-Speed IO testingSalem Abdennadher, Saghir A. Shaikh. 1-8 [doi]
- Bit-flip detection-driven selection of trace signalsAmin Vali, Nicola Nicolici. 1-6 [doi]
- On coverage of timing related faults at board levelArtur Jutman, Igor Aleksejev, Sergei Devadze. 1-2 [doi]
- IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICsErik Jan Marinissen, Teresa L. McLaurin, Hailong Jiao. 1-10 [doi]
- A new EDA flow for the mitigation of SEUs in dynamic reconfigurable FPGAsBoyang Du, Luca Sterpone, David Merodio Codinachs. 1-2 [doi]
- Transistor stuck-on fault detection tests for digital CMOS circuitsXijiang Lin, Sudhakar M. Reddy, Janusz Rajski. 1-6 [doi]
- Test-station for flexible semi-automatic wafer-level silicon photonics testingJeroen De Coster, Peter De Heyn, Marianna Pantouvaki, Brad Snyder, Hongtao Chen, Erik Jan Marinissen, Philippe Absil, Joris Van Campenhout, Bryan Bolt. 1-6 [doi]
- An optical/electrical test system for 100Gb/s optical interconnection devices with high volume testing capabilityTasuku Fujibe, Kazuki Shirahata, Takeshi Mizushima, Hidenobu Matsumura, Daisuke Watanabe, Hiroyuki Mineo, Shin Masuda. 1-2 [doi]
- The influence of hysteresis voltage on single event transients in a 65nm CMOS high speed comparatorIllani Mohd Nawi, Basel Halak, Mark Zwolinski. 1-2 [doi]
- Combining the histogram method and the ultrafast segmented model identification of linearity errors algorithm for ADC linearity testingWeida Chen, Yongxin Zhu, Xinyi Liu, Xinyang Li, Dongyu Ou. 1-2 [doi]
- Cell-aware diagnosis: Defective inmates exposed in their cellsPeter C. Maxwell, Friedrich Hapke, Huaxing Tang. 1-6 [doi]
- A low-cost susceptibility analysis methodology to selectively harden logic circuitsImran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda. 1-2 [doi]
- A self-reconfiguring IEEE 1687 network for fault monitoringFarrokh Ghani Zadegan, Dimitar Nikolov, Erik Larsson. 1-6 [doi]
- Is IoT coming to the rescue of semiconductor?Cheng-Wen Wu. 1 [doi]
- In situ measurement of aging-induced performance degradation in digital circuitsNasim Pour Aryan, Christian Funke, Jens Barsfrede, Cenk Yilniaz, Doris Schmitt-Landsiedel, Georg Georsakos. 1-2 [doi]
- Addressing transient routing errors in fault-tolerant Networks-on-ChipsAmir Charif, Nacer-Eddine Zergainoh, Michael Nicolaidis. 1-6 [doi]
- SAT-based post-processing for regional capture power reduction in at-speed scan test generationStephan Eggersglüß, Kohei Miyase, Xiaoqing Wen. 1-6 [doi]
- Automotive embedded software architecture in the multi-core agePaolo Gai, Massimo Violante. 1-8 [doi]
- A novel threshold voltage defined switch for circuit camouflagingIthihasa Reddy Nirmala, Deepak Vontela, Swaroop Ghosh, Anirudh Iyengar. 1-2 [doi]
- Failure mechanisms and test methods for the SRAM TVC write-assist techniqueJosef Kinseher, Moritz Völker, Leonardo Bonet Zordan, Ilia Polian. 1-2 [doi]
- A 40Gbps economic extension board and FPGA-based testing platformTe-Hui Chen, David C. Keezer. 1-2 [doi]
- IoT: Source of test challengesErik Jan Marinissen, Yervant Zorian, Mario Konijnenburg, Chih-Tsun Huang, Ping-Hsuan Hsieh, Peter Cockburn, Jeroen Delvaux, Vladimir Rozic, Bohan Yang 0001, Dave Singelée, Ingrid Verbauwhede, Cedric Mayor, Robert Van Rijsinge, Cocoy Reyes. 1-10 [doi]
- Read path degradation analysis in SRAMInnocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor, Wim Dehaene. 1-2 [doi]
- Securely connected vehicles - what it takes to make self-driving cars a realityLars Reger. 1 [doi]
- Group delay filter measurement using a chirpPeter Sarson. 1-2 [doi]
- A fast sweep-line-based failure pattern extractor for memory diagnosisSin-Yu Wei, Bing-Yang Lin, Cheng-Wen Wu. 1-6 [doi]
- A novel test generation and application flow for functional access to IEEE 1687 instrumentsMichele Portolan. 1-6 [doi]
- A scheduling method for hierarchical testability based on test environment generation resultsJun Nishimaki, Toshinori Hosokawa, Hideo Fujiwara. 1-2 [doi]
- Measuring defect tolerance within mixed-signal ICsStephen Sunter, Alessandro Valerio, Riccardo Miglierina. 1-2 [doi]
- Cell Aware and stuck-open testsAdit D. Singh. 1-6 [doi]
- Compressor design for silicon debugJing Zhang, Lars-Johan Fritz, Liang Liu, Erik Larsson. 1-2 [doi]
- A design-for-test solution for monolithic 3D integrated circuitsRan Wang, Krishnendu Chakrabarty. 1-6 [doi]
- A hybrid algorithm to conservatively check the robustness of circuitsNiels Thole, Lorena Anghel, Görschwin Fey. 1-2 [doi]
- ETS 2015 best paperHans-Joachim Wunderlich, Peter C. Maxwell. 1 [doi]
- Questioning the reliability of Monte Carlo simulation for machine learning test validationGildas Leger, Manuel J. Barragan. 1-6 [doi]
- CPE: Codeword Prediction EncoderSatish Grandhi, Elsa Dupraz, Christian Spagnol, Valentin Savin, Emanuel M. Popovici. 1-2 [doi]
- Component fault localization using switching current measurementsSeetal Potluri, Satya Trinadh, Siddhant Saraf, Kamakoti Veezhinathan. 1-2 [doi]
- Two-dimensional time-division multiplexing for 3D-SoCsPanagiotis Georgiou, Fotios Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty. 1-6 [doi]
- IJTAG supported 3D DFT using chiplet-footprints for testing multi-chips active interposer systemJean Durupt, Pascal Vivet, Juergen Schloeffel. 1-6 [doi]
- Study of a delayed single-event effect in the Muller C-elementVaradan Savulimedu Veeravalli, Andreas Steininger. 1-2 [doi]
- Behavior and test of open-gate defects in FinFET based cellsFrancisco Mesalles, Hector Villacorta, Michel Renovell, Víctor H. Champac. 1-6 [doi]
- Utilizing shared memory multi-cores to speed-up the ATPG processStavros Hadjitheophanous, Stelios N. Neophytou, Maria K. Michael. 1-6 [doi]
- Cross-layer resilienceSubhasish Mitra. 1 [doi]
- Testing in the year 2024 - big changes are comingPhil Nigh. 1 [doi]
- Reliability enhancement of embedded memory with combination of aging-aware adaptive in-field self-repair and ECCGian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato, Michiko Inoue. 1-2 [doi]
- A built-in method for measuring the delay of TSVs in 3D ICsHan-Yu Wu, Yong-Xiao Chen, Jin-Fu Li. 1-6 [doi]
- Formal verification of secure reconfigurable scan network infrastructureMichael A. Kochte, Rafal Baranowski, Matthias Sauer, Bernd Becker, Hans-Joachim Wunderlich. 1-6 [doi]
- Testing of small delay faults in a clock networkShaofu Yang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng. 1-6 [doi]
- ETS 2016 forewordSaid Hamdioui, Giorgio Di Natale, Bram Kruseman, Maria K. Michael, Haralampos-G. D. Stratigopoulos. 1 [doi]
- On the diagnostic analysis of IEEE 1687 networksRiccardo Cantoro, Mehrdad Montazeri, Matteo Sonza Reorda, Farrokh Ghani Zadegan, Erik Larsson. 1-2 [doi]
- Analysis and design of an on-chip retargeting engine for IEEE 1687 networksAhmed Ibrahim, Hans G. Kerkhoff. 1-6 [doi]
- VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllersSebastian Huhn, Stephan Eggersglüß, Rolf Drechsler. 1-6 [doi]
- Analysis of electrostatic coupling in monolithic 3D integrated circuits and its impact on delay testingAbhishek Koneru, Krishnendu Chakrabarty. 1-6 [doi]