Abstract is missing.
- Efficient multilevel formal analysis and estimation of design vulnerability to Single Event TransientsGhaith Bany Hamad, Otmane Aït Mohamed, Yvon Savaria. 1-6 [doi]
- Bayesian network early reliability evaluation analysis for both permanent and transient faultsAlessandro Vallero, Alessandro Savino, Sotiris Tselonis, Nikos Foutris, Manolis Kaliorakis, Gianfranco Politano, Dimitris Gizopoulos, Stefano Di Carlo. 7-12 [doi]
- Laser fault injection into SRAM cells: Picosecond versus nanosecond pulsesMarc Lacruche, Nicolas Borrel, Clement Champeix, Cyril Roscian, Alexandre Sarafianos, Jean-Baptiste Rigaud, Jean-Max Dutertre, Edith Kussener. 13-18 [doi]
- A call for cross-layer and cross-domain reliability analysis and managementDan Alexandrescu, Adrian Evans, Enrico Costenaro, Maximilien Glorieux. 19-22 [doi]
- An accurate soft error propagation analysis technique considering temporal masking disablementYuta Kimi, Go Matsukawa, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto. 23-25 [doi]
- An Hybrid Architecture for consolidating mixed criticality applications on multicore systemsSerhiy Avramenko, Stefano Esposito, Massimo Violante, Marco Sozzi, Massimo Traversone, Marco Binello, Marco Terrone. 26-29 [doi]
- Fault modeling and testing of through silicon via interconnectionsVasileios Gerakis, Leonidas Katselas, Alkis A. Hatzopoulos. 30-31 [doi]
- Identifying aging-aware representative paths in processorsChiara Sandionigi, Olivier Héron. 32-33 [doi]
- On the maximization of the sustained switching activity in a processorRiccardo Cantoro, Matteo Sonza Reorda, Alireza Rohani, Hans G. Kerkhoff. 34-35 [doi]
- Optimization of SEU emulation on SRAM FPGAs based on sensitiveness analysisAnis Souari, Claude Thibeault, Yves Blaquière, Raoul Velazco. 36-39 [doi]
- Power analysis attacks on ARX: An application to Salsa20Bodhisatwa Mazumdar, Sk Subidh Ali, Ozgur Sinanoglu. 40-43 [doi]
- Simplification of fully delay testable combinational circuitsAnzhela Matrosova, Eugeniy Mitrofanov, Toral Shah. 44-45 [doi]
- Soft error immune latch under SEU related double-node charge collectionKaterina Katsarou, Yiorgos Tsiatouhas. 46-49 [doi]
- Towards Trojan circuit detection with maximum state transition explorationJoseph Lenox, Spyros Tragoudas. 50-52 [doi]
- Concurrent error detection in nonlinear digital filters using checksum linearization and residue predictionSuvadeep Banerjee, Md Imran Momtaz, Abhijit Chatterjee. 53-58 [doi]
- Adaptive healing procedure for lifetime improvement in Wireless Sensor NetworksDiane Tchuani Tchakonte, Emmanuel Simeu, Maurice Tchuente. 59-64 [doi]
- Fault-tolerant system for catastrophic faults in AMR sensorsAndreina Zambrano, Hans G. Kerkhoff. 65-70 [doi]
- MUGEN: A high-performance fault-tolerant routing algorithm for unreliable Networks-on-ChipAmir Charif, Nacer-Eddine Zergainoh, Michael Nicolaidis. 71-76 [doi]
- Timing-resilient Network-on-Chip architecturesAlexandros Panteloukas, Anastasios Psarras, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos. 77-82 [doi]
- Defect diagnosis algorithms for a field programmable interconnect network embedded in a Very Large Area Integrated CircuitGontran Sion, Yves Blaquière, Yvon Savaria. 83-88 [doi]
- Design space exploration and optimization of a Hybrid Fault-Tolerant ArchitectureI. Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda. 89-94 [doi]
- Efficient on-line fault-tolerance for the preconditioned conjugate gradient methodAlexander Scholl, Claus Braun, Michael A. Kochte, Hans-Joachim Wunderlich. 95-100 [doi]
- Mitigation of fail-stop failures in integer matrix products via numerical packingIjeoma Anarado, Yiannis Andreopoulos. 101-107 [doi]
- The future of fault tolerant computingJacob A. Abraham, Ravishankar Iyer, Dimitris Gizopoulos, Dan Alexandrescu, Yervant Zorian. 108-109 [doi]
- Toward efficient check-pointing and rollback under on-demand SBST in chip multi-processorsMichael A. Skitsas, Chrysostomos Nicopoulos, Maria K. Michael. 110-115 [doi]
- Workload characterization and prediction: A pathway to reliable multi-core systemsMonir Zaman, Ali Ahmadi, Yiorgos Makris. 116-121 [doi]
- Failure mitigation in linear, sesquilinear and bijective operations on integer data streams via numerical entanglementMohammad Ashraful Anam, Yiannis Andreopoulos. 122-127 [doi]
- Self-awareness and self-learning for resiliency in real-time systemsMehdi Baradaran Tahoori, Abhijit Chatterjee, Krishnendu Chakrabarty, Abhishek Koneru, Arunkumar Vijayan, Debashis Banerjee. 128-131 [doi]
- Filtering-based error-tolerability evaluation of image processing circuitsTong-Yu Hsieh, Yi-Han Peng. 132-137 [doi]
- A single chip dependable and adaptable payload Data Processing UnitNektarios Kranitis, Antonis Tsigkanos, George Theodorou, Ioannis Sideris, Antonis M. Paschalis. 138-143 [doi]
- Characterizing fault propagation in safety-critical processor designsJaime Espinosa, Carles Hernández, Jaume Abella. 144-149 [doi]
- Experimental validation of a Bulk Built-In Current Sensor for detecting laser-induced currentsClement Champeix, Nicolas Borrel, Jean-Max Dutertre, Bruno Robisson, Mathieu Lisart, Alexandre Sarafianos. 150-155 [doi]
- OPUF: Obfuscation logic based physical unclonable functionJing Ye, Yu Hu, Xiaowei Li 0001. 156-161 [doi]
- Flip-flop SEU reduction through minimization of the temporal vulnerability factor (TVF)Adrian Evans, Enrico Costenaro, Arkady Bramnik. 162-167 [doi]
- An effective embedded test & diagnosis solution for external memoriesGurgen Harutunyan, Yervant Zorian. 168-170 [doi]
- Low-power memory repair for high defect densitiesPanagiota Papavramidou, Michael Nicolaidis. 171-173 [doi]
- Reliability/yield trade-off in mitigating "no trouble found" field returnsAmr Haggag, Nik Sumikawa, Aamer Shaukat. 174-175 [doi]
- Efficient observation point selection for aging monitoringChang Liu, Michael A. Kochte, Hans-Joachim Wunderlich. 176-181 [doi]
- Mining simulation metrics for failure triage in regression testingZissis Poulos, Andreas G. Veneris. 182-187 [doi]
- Real-time on-chip supply voltage sensor and its application to trace-based timing error localizationMiho Ueno, Masanori Hashimoto, Takao Onoye. 188-193 [doi]
- BTI and leakage aware dynamic voltage scaling for reliable low power cache memoriesDaniele Rossi, Vasileios Tenentes, S. Saqib Khursheed, Bashir M. Al-Hashimi. 194-199 [doi]
- New byte error correcting codes with simple decoding for reliable cache designLake Bu, Mark G. Karpovsky, Zhen Wang. 200-205 [doi]
- Low leakage radiation tolerant CAM/TCAM cellNikolaos Eftaxiopoulos-Sarris, Nicholas Axelos, Kiamal Z. Pekmestzi. 206-211 [doi]