Table of Contents

• Variation Aware Design of Post-Silicon Tunable Clock BufferVikram B. Suresh, Wayne P. Burleson. 1-6 [doi]
• Framework of an Adaptive Delay-Insensitive Asynchronous Platform for Energy EfficiencyLiang Men, Brent Hollosi, Jia Di. 7-12 [doi]
• Regulator-Gating Methodology with Distributed Switched Capacitor Voltage ConvertersOrhun Aras Uzun, Selçuk Köse. 13-18 [doi]
• Design-for-Security vs. Design-for-Testability: A Case Study on DFT Chain in Cryptographic CircuitsYier Jin. 19-24 [doi]
• PUF Interfaces and their SecurityMarten van Dijk, Uli Ruhrmair. 25-28 [doi]
• Post-Silicon Validation and Calibration of Hardware Security PrimitivesXiaolin Xu, Vikram B. Suresh, Raghavan Kumar, Wayne P. Burleson. 29-34 [doi]
• Design of a Flexible, Energy Efficient (Auto)Correlator Block for Timing SynchronizationFabio Campi, Roberto Airoldi, Jari Nurmi. 35-40 [doi]
• A Novel Class of Linear MIMO Detectors with Boosted Communications Performance: Algorithm and VLSI ArchitectureDominik Auras, Rainer Leupers, Gerd Ascheid. 41-47 [doi]
• Experiments with High Speed Parallel Cubing UnitsSon Bui, James E. Stine, Masoud Sadeghian. 48-53 [doi]
• A Chaos-Based Arithmetic Logic Unit and Implications for ObfuscationGarrett Steven Rose. 54-58 [doi]
• Trust No One: Thwarting "heartbleed" Attacks Using Privacy-Preserving ComputationNektarios Georgios Tsoutsos, Michail Maniatakos. 59-64 [doi]
• A Weighted Sensing Scheme for ReRAM-Based Cross-Point Memory ArrayChenchen Liu, Hai Li. 65-70 [doi]
• FuzzRoute: A Method for Thermally Efficient Congestion Free Global Routing in 3D ICsDebashri Roy, Prasun Ghosal, Saraju P. Mohanty. 71-76 [doi]
• Neuromemristive Extreme Learning Machines for Pattern ClassificationCory E. Merkel, Dhireesha Kudithipudi. 77-82 [doi]
• A New Walsh Hadamard Transform Architecture Using Current Mode CircuitSwagata Bhattacharya, Somsubhra Talapatra. 83-88 [doi]
• A Transient-Enhanced Capacitorless LDO Regulator with improved Error AmplifierSuresh Alapati, Patri SrihariRao, K. S. R. Krishna Prasad, Saurabh Dixit. 89-93 [doi]
• Memristor Crossbar Based Programmable InterconnectsRaqibul Hasan, Tarek M. Taha. 94-99 [doi]
• Automatic Handling of Conflicts in Synchronous Interpreted Time Petri Nets ImplementationHelene Leroux, Karen Godary-Dejean, Guillaume Coppey, David Andreu. 100-105 [doi]
• Swarm Intelligence Driven Simultaneous Adaptive Exploration of Datapath and Loop Unrolling Factor during Area-Performance TradeoffAnirban Sengupta, Vipul Kumar Mishra. 106-111 [doi]
• Slicing Floorplans with Handling Symmetry and General Placement ConstraintsHongxia Zhou, Chiu-Wing Sham, Hailong Yao. 112-117 [doi]
• Physical vs. Physically-Aware Estimation Flow: Case Study of Design Space Exploration of AddersIvan Ratkovic, Oscar Palomar, Milan Stanic, Osman S. Unsal, Adrián Cristal, Mateo Valero. 118-123 [doi]
• Data Correlation Aware Serial Encoding for Low Switching Power On-Chip CommunicationSomrita Ghosh, Prasun Ghosal, Nabanita Das, Saraju P. Mohanty, Oghenekarho Okobiah. 124-129 [doi]
• Computational Architectures Based on Coupled OscillatorsMatthew J. Cotter, Yan Fang, Steven P. Levitan, Donald M. Chiarulli, Vijaykrishnan Narayanan. 130-135 [doi]
• A Low Latency Scalable 3D NoC Using BFT Topology with Table Based Uniform RoutingAvik Bose, Prasun Ghosal, Saraju P. Mohanty. 136-141 [doi]
• An Algorithm for Parallel Assay Operations in a Restricted Sized Chip in Digital MicrofluidicsDebasis Dhal, Piyali Datta, Arpan Chakrabarty, Goutam Saha, Rajat Kumar Pal. 142-147 [doi]
• Analytical Model for Inverter Design Using Floating Gate Graphene Field Effect TransistorsAtul Kumar Nishad, Aditya Dalakoti, Ashish Jindal, Rahul Kumar, Somesh Kumar, Rohit Sharma. 148-153 [doi]
• Modeling the Impact of TSVs on Average Wire Length in 3DICs Using a Tier-Level Hierarchical ApproachNeela Gopi, Jeffrey Draper. 154-159 [doi]
• Removing the Root of Trust: Secure Oblivious Key Establishment for FPGAsLei Xu, Weidong Shi. 160-165 [doi]
• Reconfigurable Dynamic Trusted Platform Module for Control Flow CheckingSanjeev Das, Wei Zhang, Yang Liu. 166-171 [doi]
• Patterned Heterogeneous CMPs: The Case for Regularity-Driven System-Level SynthesisNikita Nikitin, Magnus Jahre. 172-177 [doi]
• Energy-Aware Thread Scheduling for Embedded Multi-threaded Processors: Architectural Level Design and ImplementationMahanama Wickramasinghe, Hui Guo. 178-183 [doi]
• An Efficient Hardware Implementation of DVFS in Multi-core System with Wireless Network-on-ChipHemanta Kumar Mondal, Gade Narayana Sri Harsha, Sujay Deb. 184-189 [doi]
• A Broadcast-Enabled Sensing System for Embedded Multi-core ProcessorsJia Zhao, Shiting Justin Lu, Wayne P. Burleson, Russell Tessier. 190-195 [doi]
• Session Based Core Test Scheduling for 3D SOCsSurajit Kumar Roy, Payel Ghosh, Hafizur Rahaman, Chandan Giri. 196-201 [doi]
• On Designing Robust Path-Delay Fault Testable Combinational Circuits Based on Functional PropertiesRupali Mitra, Debesh K. Das, Bhargab B. Bhattacharya. 202-207 [doi]
• Cost-Effective Test Optimized Scheme of TSV-Based 3D SoCs for Pre-Bond TestKele Shen, Dong Xiang, Zhou Jiang. 208-213 [doi]
• Impact of Process Variations on Reliability and Performance of 32-nm 6T SRAM at Near Threshold VoltageLingbo Kou, William H. Robinson. 214-219 [doi]
• A Low-Power Enhanced Bitmask-Dictionary Scheme for Test Data CompressionVahid Janfaza, Payman Behnam, Bahjat Forouzandeh, Bijan Alizadeh. 220-225 [doi]
• A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply NoiseAnu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel. 226-231 [doi]
• Enabling Side Channel Secure FSMs in the Presence of Low Power RequirementsMike Borowczak, Ranga Vemuri. 232-235 [doi]
• Dynamic Phase-Based Optimization of Embedded SystemsTosiron Adegbija, Ann Gordon-Ross. 236-239 [doi]
• A Low-Cost and High-Performance Embedded System Architecture and an Evaluation MethodologyXiaokun Yang, Jean H. Andrian. 240-243 [doi]
• Exploring Kriging for Fast and Accurate Design Optimization of Nanoscale Analog CircuitsOghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos. 244-247 [doi]
• Exploration of Magnetic RAM Based Memory Hierarchy for Multicore ArchitectureSophiane Senni, Lionel Torres, Gilles Sassatelli, Anastasiia Butko, Bruno Mussard. 248-251 [doi]
• Theory, Synthesis, and Application of Adiabatic and Reversible Logic Circuits for Security ApplicationsMatthew Morrison. 252-255 [doi]
• A Low-Noise Variable-Gain Amplifier for in-Probe 3D Imaging Applications Based on CMUT TransducersHourieh Attarzadeh, Trond Ytterdal. 256-260 [doi]
• A CMOS Temperature Sensor with -0.34°C to 0.27°C Inaccuracy from -30°C to 80°CHai Chi, Tom Chen. 261-266 [doi]
• A Compact CMOS Ring Oscillator with Temperature and Supply Compensation for Sensor ApplicationsYanmei Wang, Pak Kwong Chan, King Ho Li. 267-272 [doi]
• Variation-Aware Analysis and Test Pattern Generation Based on Functional FaultsMasahiro Fujita. 273-277 [doi]
• Where is the Achilles Heel under Circuit AgingKetul Sutaria, Athul Ramkumar, Rongjun Zhu, Yu Cao. 278-279 [doi]
• Chip Health Monitoring Using Machine LearningFarshad Firouzi, Fangming Ye, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori. 280-283 [doi]
• Toward Holistic Modeling, Margining and Tolerance of IC VariabilityAndrew B. Kahng. 284-289 [doi]
• FinCACTI: Architectural Analysis and Modeling of Caches with Deeply-Scaled FinFET DevicesAlireza Shafaei, Yanzhi Wang, Xue Lin, Massoud Pedram. 290-295 [doi]
• Independently-Controlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access SpeedKaisheng Ma, Huichu Liu, Yang Xiao, Yang Zheng, Xueqing Li, Sumeet Kumar Gupta, Yuan Xie 0001, Vijaykrishnan Narayanan. 296-301 [doi]
• A Low-Voltage Low-Power LC Oscillator Using the Diode-Connected SymFETXueqing Li, Wei-Yu Tsai, Huichu Liu, Suman Datta, Vijaykrishnan Narayanan. 302-307 [doi]
• FDPIC: Generation of Functional Test Sequences Based on Fault-Dependent Primary Input CubesIrith Pomeranz. 308-313 [doi]
• OBO: An Output-by-Output Scoring Algorithm for Fault DiagnosisIrith Pomeranz. 314-319 [doi]
• Diagnosis of Gate Delay Faults in the Presence of Clock Delay FaultsYoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja. 320-325 [doi]
• Layout-Aware Selection of Trace Signals for Post-Silicon DebugPrateek Thakyal, Prabhat Mishra. 326-331 [doi]
• Configurable Architecture for Double/Two-Parallel Single Precision Floating Point DivisionManish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul. 332-337 [doi]
• Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic CircuitsFarimah Farahmandi, Bijan Alizadeh, Zainalabedin Navabi. 338-343 [doi]
• Improving GA-Based NoC Mapping Algorithms Using a Formal ModelVinitha Arakkonam Palaniveloo, Jude Angelo Ambrose, Arcot Sowmya. 344-349 [doi]
• Simultaneous Two-Dimensional Cell Layout Compaction Using MILP with ASTRANAdriel Mota Ziesemer, Ricardo Augusto da Luz Reis. 350-355 [doi]
• Function Extraction from Arithmetic Bit-Level CircuitsMaciej J. Ciesielski, Walter Brown, Duo Liu, André Rossi. 356-361 [doi]
• Buffering Single-Walled Carbon Nanotubes Bundle Interconnects for Timing OptimizationLin Liu, Yuchen Zhou, Shiyan Hu. 362-367 [doi]
• Characterization of MWCNT VLSI Interconnect with Self-Heating Induced ScatteringsK. M. Mohsin, Ashok Srivastava, Ashwani K. Sharma, Clay Mayberry. 368-373 [doi]
• High Mobility n and p Channels on Gallium Arsenide and Silicon Substrates Using Interfacial Misfit Dislocation ArraysDarryl Shima, Ganesh Balakrishnan. 374-379 [doi]
• Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational CircuitsJiaoyan Chen, Christian Spagnol, Satish Grandhi, Emanuel M. Popovici, Sorin Cotofana, Alexandru Amaricai. 380-385 [doi]
• 2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT ArchitecturesYassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, Juergen Schloeffel. 386-391 [doi]
• HARS: A High-Performance Reliable Routing Scheme for 3D NoCsJun Zhou, Huawei Li, Yuntan Fang, Tiancheng Wang, Yuanqing Cheng, Xiaowei Li 0001. 392-397 [doi]
• Computing with Spin-Transfer-Torque Devices: Prospects and PerspectivesKaushik Roy, Mrigank Sharad, Deliang Fan, Karthik Yogendra. 398-402 [doi]
• Unlocking Controllable-Polarity Transistors Opportunities by Exclusive-OR and Majority Logic SynthesisPierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Giovanni De Micheli. 403-405 [doi]
• Memristor Modeling - Static, Statistical, and Stochastic MethodologiesHai Li, Miao Hu, Chuandong Li, Shukai Duan. 406-411 [doi]
• Mach-Zehnder Interferometer Based All Optical Reversible Carry-Lookahead AdderPratik Dutta, Chandan Bandyopadhyay, Chandan Giri, Hafizur Rahaman. 412-417 [doi]
• Perfomance Improvement with Dedicated Transistor Sizing for MOSFET and FinFET DevicesGracieli Posser, Jozeanne Belomo, Cristina Meinhardt, Ricardo Augusto da Luz Reis. 418-423 [doi]
• 5nm FinFET Standard Cell Library Optimization and Circuit Synthesis in Near-and Super-Threshold Voltage RegimesQing Xie, Xue Lin, Yanzhi Wang, Mohammad Javad Dousti, Alireza Shafaei, Majid Ghasemi-Gol, Massoud Pedram. 424-429 [doi]
• A Feedback, Runtime Technique for Scaling the Frequency in GPU ArchitecturesYue Wang, Nagarajan Ranganathan. 430-435 [doi]
• Reducing Energy per Instruction via Dynamic Resource Allocation and Voltage and Frequency Adaptation in Asymmetric MulticoresArunachalam Annamalai, Rance Rodrigues, Israel Koren, Sandip Kundu. 436-441 [doi]
• System-Level Power and Energy Estimation Methodology for Open Multimedia Applications PlatformsSanthosh Kumar Rethinagiri, Oscar Palomar, Javier Arias Moreno, Osman S. Unsal, Adrián Cristal, Morteza Biglari-Abhari. 442-449 [doi]
• Robustness Analysis of Real-Time Scheduling Against Differential Power Analysis AttacksKe Jiang, Lejla Batina, Petru Eles, Zebo Peng. 450-455 [doi]
• Moving Network Protection from Software to Hardware: An Energy Efficiency AnalysisAndre Luiz Pereira de Franca, Ricardo Pereira Jasinski, Volnei Antonio Pedroni, Altair Olivo Santin. 456-461 [doi]
• Achieving High-Performance Video Analytics with Lightweight Cores and a Sea of Hardware AcceleratorsKevin M. Irick, Nandhini Chandramoorthy. 462-467 [doi]
• Low Power and Scalable Many-Core Architecture for Big-Data Stream ComputingKarim Kanoun, Martino Ruggiero, David Atienza, Mihaela van der Schaar. 468-473 [doi]
• Big Data Processing with FPGA Supercomputers: Opportunities and ChallengesApostolos Dollas. 474-479 [doi]
• A Case Study on the Communication and Computation Behaviors of Real Applications in NoC-Based MPSoCsZhe Wang, Weichen Liu, Jiang Xu, Bin Li, Ravi Iyer, Ramesh Illikkal, Xiaowen Wu, Wai Ho Mow, Wenjing Ye. 480-485 [doi]
• Network-on-Chip Design for Heterogeneous Multiprocessor System-on-ChipBharath Phanibhushana, Sandip Kundu. 486-491 [doi]
• Towards an Effective Utilization of Partially Defected Interconnections in 2D Mesh NoCsChanglin Chen, Sorin Dan Cotofana. 492-497 [doi]
• High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop DesignCan Sitik, Leo Filippini, Emre Salman, Baris Taskin. 498-503 [doi]
• Glitch Power Reduction via Clock Skew SchedulingArunkumar Vijayakumar, Sandip Kundu. 504-509 [doi]
• On Maximizing Decoupling Capacitance of Clock-Gated Logic for Robust Power DeliveryArunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu. 510-515 [doi]
• Towards Secure Analog Designs: A Secure Sense Amplifier Using MemristorsDavid H. K. Hoe, Jeyavijayan Rajendran, Ramesh Karri. 516-521 [doi]
• Glitch Resistant Private Circuits Design Using HORNSMahadevan Gomathisankaran, Akhilesh Tyagi. 522-527 [doi]
• Towards Making Private Circuits Practical: DPA Resistant Private CircuitsJungmin Park, Akhilesh Tyagi. 528-533 [doi]
• LastingNVCache: A Technique for Improving the Lifetime of Non-volatile CachesSparsh Mittal, Jeffrey S. Vetter, Dong Li. 534-540 [doi]
• A Reconfigurable Architecture for QR Decomposition Using a Hybrid ApproachXinying Wang, Phillip H. Jones, Joseph Zambreno. 541-546 [doi]
• An Improved Thermal Model for Static Optimization of Application Mapping and Scheduling in Multiprocessor System-on-ChipJuan Yi, Weichen Liu, Weiwen Jiang, Mingwen Qin, Lei Yang, Duo Liu, Chunming Xiao, Luelue Du, Edwin Hsing-Mean Sha. 547-552 [doi]
• Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGASaif-Ur Rehman, Adrien Blanchardon, Arwa Ben Dhia, Mounir Benabdenbi, Roselyne Chotin-Avot, Lirida A. B. Naviner, Lorena Anghel, Habib Mehrez, Emna Amouri, Zied Marrakchi. 553-558 [doi]
• SET Susceptibility Analysis of Clock Tree and Clock Mesh TopologiesRaul Chipana, Fernanda Gusmão de Lima Kastensmidt. 559-564 [doi]
• Processor Design with Asymmetric ReliabilityZheng Wang, Goutam Paul, Anupam Chattopadhyay. 565-570 [doi]
• "Green" On-chip Inductors in Three-Dimensional Integrated CircuitsUmamaheswara Rao Tida, Varun Mittapalli, Cheng Zhuo, Yiyu Shi. 571-576 [doi]
• Mitigating NBTI Degradation on FinFET GPUs through Exploiting Device HeterogeneityYing Zhang, Sui Chen, Lu Peng, Shaoming Chen. 577-582 [doi]
• Multi-level, Memory-Based Logic Using CMOS TechnologyIndira Priyadarshini Dugganapally, Steve E. Watkins, Benjamin Cooper. 583-588 [doi]
• Alternative Standard Cell Placement Strategies for Single-Event Multiple-Transient MitigationBradley T. Kiddie, William H. Robinson. 589-594 [doi]
• Methodical Design Approaches to Radiation Effects Analysis and Mitigation in Flip-Flop CircuitsLawrence T. Clark, Sandeep Shambhulingaiah. 595-600 [doi]
• Low Power Soft Error Tolerant Macro Synchronous Micro Asynchronous (MSMA) PipelineFaiq Khalid Lodhi, Syed Rafay Hasan, Osman Hasan, Falah Awwad. 601-606 [doi]
• A Fast Hypergraph Bipartitioning AlgorithmWenzan Cai, Evangeline F. Y. Young. 607-612 [doi]
• A Graph-Based 3D IC Partitioning TechniqueSabyasachee Banerjee, Subhashis Majumder, Bhargab B. Bhattacharya. 613-618 [doi]
• Parallel Multi-core Verilog HDL Simulation Using Domain PartitioningTariq B. Ahmad, Maciej J. Ciesielski. 619-624 [doi]