Table of Contents

• IEA-Plugin: An AI Agent Reasoner for Test Data AnalyticsSeoyeon Kim, Yu Su, Li-C. Wang. 1-10 [doi]
• Scan Test for 99% Defect Coverage of R-2R DACsStephen Sunter, Krzysztof Jurga. 11-18 [doi]
• Defect-Finding with Timing-Partitioned Small-Delay-Defect Methodology: Silicon Practice on N2Hao-Yu Yang, Hsin-Wei Hung, Nan-Hsin Tseng. 19-26 [doi]
• Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability AnalysisQuan Cheng, Hao-Yang Chi, Chien-Hsing Liang, Yu-Hong Chao, Huizi Zhang, Yuan Liang, Mingtao Zhang, Wang Liao, Jinjun Xiong, Jing-Jia Liou, Masanori Hashimoto, Longyang Lin. 27-36 [doi]
• Chiplets' Die-to-Die Interconnect Repair Language (IRL)Po-Yao Chuang, Erik Jan Marinissen. 37-44 [doi]
• TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM CollaborationZhiteng Chao, Rengang Zhang, Feng Gu, Hongqin Lyu, Bin Sun, Wenxing Li, Zizhen Liu, Jianan Mu, Jing Ye 0001, Xiaowei Li 0001, Huawei Li 0001. 45-52 [doi]
• QuEST: Quantitative Entropy based Security and Trojan Detection Framework for Confidentiality VerificationJiaming Wu, Domenic Forte. 53-62 [doi]
• Push-on mating 57- to 81- GHz mm-Wave interface with high repeatability for ATE applicationMinoru Iida, Norio Kobayashi, Hideki Shirasu, Masayuki Nakamura. 63-71 [doi]
• Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay InsertionCheng En Chung, Jun-Han Jian, Kuen-Jong Lee, Nan-Hsin Tseng, Hsin-Wei Hung, Hao-Yu Yang, Dong-Yi Chen. 72-81 [doi]
• Chain Cell-Aware DiagnosisSzczepan Urban, Jakub Janicki, Piotr Zimnowlodzki, Artur Stelmach, Manish Sharma. 82-91 [doi]
• Enhancing Timing Predictability in Automotive Electronics: Addressing Aging and Temperature DistributionsJeffery Y.-C. Chen, Jason W.-Y. Cheng, Aaron C.-W. Liang, Charles H.-P. Wen, Gung-Yu Pan, Hen-Ming Lin. 92-101 [doi]
• Stress Aware Quiescent Current Test OptimizationShubhendu Shrivastava, Jo Gunnes, Anteneh Gebregiorgis, Said Hamdioui. 102-110 [doi]
• Persistent High-Bandwidth IJTAG Data DeliveryJan Burchard, Matthias Kampmann, Ayush Patel, Marta Stepniewska, Przemyslaw Szymanski, Wojciech Janiszewski, Jean-François Côté, Michal Olejarz, Olga Przybysz, Lori Schramm, Jonathan Gaudet, Martin Keim. 111-120 [doi]
• LLM-Aided In-Field Workload Generation for Detecting Silent Data Corruptions at ScalePeter Domanski, Deepesh Sahoo, Eduardo Ortega, Farshad Firouzi, Krishnendu Chakrabarty. 121-130 [doi]
• OCTANE: On-Chip Telemetry-based Anomaly Notification EngineEduardo Ortega, Arjun Hati, Jonti Talukdar, Woohyun Paik, Fei Su, Rita Chattopadhyay, Krishnendu Chakrabarty. 131-140 [doi]
• LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Pattern Generation for Zero Defect Automotive DesignsMohammed Zine E. Brahmi, Jennifer Dworak, Martina Perkovic, Megan Appel, Saidapet Ramesh, Ravi J. N, Ramanath Dharmavarm, Arun Kumar Anjaneyareddy, Chen He. 141-150 [doi]
• Automated Selection of Optimal EDT Input ConfigurationGrzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer. 151-160 [doi]
• NeuralTPG: GPU-Accelerated Neural Twin-Based Test Pattern Generation for Transition Delay Faults in Safety-Critical ApplicationsXuanyi Tan, Gitanjali Mukherjee, Dhruv Thapar, Arjun Chaudhuri, Sanmitra Banerjee, Rubin A. Parekhji, Krishnendu Chakrabarty. 161-170 [doi]
• A Novel Omnidirectional 3D Test Access Architecture for Advanced System-on-Wafer (SoW) ApplicationsHiroyuki Iwata, Sandeep Kumar Goel, Ankita Patidar, Fumiaki Takashima, Frank Lee 0004. 171-180 [doi]
• A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAMMin-Kyu Kim, Incheol Nam, Minju Shin, Kyungrak Cho, Gijong Sung, Deasun Kim, Heeil Hong, Sangjoon Hwang. 181-185 [doi]
• A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault AnalysisChien-Hsing Liang, Yu-Hong Chao, Jing-Jia Liou, Harry H. Chen. 186-195 [doi]
• Debugging and Preventing Abnormally High Vmin during Logic Scan Test Bring-upMin-Hsin Liu, Ding-Wei Cheng, James Chien-Mo Li, Chris Nigh, Szu Huat Goh, Mason Chern, Bing-Han Hsieh, Subhadip Kundu. 196-205 [doi]
• Advanced fault model, diagnosis and applications for deep nanometer processYoungseok Son, Muyun Cho, Hyunyul Lim, Jaeseok Park, Piotr Zimnowlodzki, Szczepan Urban, Jayant D'Souza, Manish Sharma. 206-212 [doi]
• Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory ArchitecturesAli Nezhadi, Odysseas Chatzopoulos, Mahta Mayahinia, George Papadimitriou 0001, Mehdi Baradaran Tahoori, Dimitris Gizopoulos. 213-222 [doi]
• Functional Test Generation for In-Field Testing of Deep Learning Models with Test Storage ConstraintsDina A. Moussa, Michael Hefenbrock, Mehdi B. Tahoori. 223-232 [doi]
• Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)Behnam Farnaghinejad, Davide Bellizia, Alessandra Dolmeta, Guido Masera, Antonio Porsia, Annachiara Ruospo, Stefano Di Carlo, Alessandro Savino, Ernesto Sánchez 0001. 233-242 [doi]
• Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan NetworksSebastian Huhn, Matthias Kampmann, Jan Burchard, Reinhard Meier, Kacper Czerniawski, Lori Schramm, Sandipan Sharma, Nikita Naresh, Wilson Pradeep, Prachi Sinha, Mayank Parasrampuria, Jonathan Gaudet, Martin Keim. 243-252 [doi]
• DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious ErrorsSuriyaprakash Natarajan, Chaitali S. Oak, Nipun Chaplot, Vijay Kakollu, Venkata A. R. Gurram, Manish J. Mishra, Fayez Abu-gosh. 253-261 [doi]
• Silicon Photonic Test-Point Selection by Integrating Design Parameters with Hypergraph PartitioningLawrence M. Schlitt, Pratishtha Agnihotri, Priyank Kalla, Steve Blair. 262-271 [doi]
• Ultra dense SRAM Cell Test ChallengesUma Srinivasan 0002, William V. Huott, Austen Hall, Ryan Thorpe, Daniel Rodko, Greg Hornicek, Brian Noble. 272-280 [doi]
• Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault DominanceGowsika Dharmaraj, Abhijit Chatterjee, Adit D. Singh, Arani Sinha. 281-290 [doi]
• Making IJTAG Address Physical-World Digital and Mixed-Signal Test ChallengesHans Martin von Staudt, Jeff Rearick, Michael Laisne. 291-300 [doi]
• IC-PEPR: PEPR Testing Goes Intra-CellChris Nigh, Ruben Purdy, Wei Li, Subhasish Mitra, R. D. (Shawn) Blanton. 301-309 [doi]
• *Partho Bhoumik, Dhruv Thapar, Arjun Chaudhuri, Krishnendu Chakrabarty. 310-319 [doi]
• Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized ActivationSoyed Tuhin Ahmed, Eduardo Ortega, Ryan Depsey, T. Patrick Xiao, Ben Feinberg, Christopher H. Bennett, Matthew J. Marinella, Krishnendu Chakrabarty. 320-329 [doi]
• Scan Chain Diagnosis in Advanced Process Nodes: The Art of Balancing Resolution, Repairability, and CostSandeep Kumar Goel, Ankita Patidar, Yue Tian, Frank Lee 0004. 330-338 [doi]
• LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test EfficiencySudipta Paria, Md Rezoan Ferdous, Aritra Dasgupta 0002, Atri Chatterjee, Swarup Bhunia. 339-348 [doi]
• Transfer Learning for Minimum Operating Voltage Prediction in Advanced Technology Nodes: Leveraging Legacy Data and Silicon Odometer SensingYuxuan Yin, Rebecca Chen, Boxun Xu, Chen He, Peng Li 0001. 349-356 [doi]
• *Partho Bhoumik, Arjun Chaudhuri, Sandeep Kumar Goel, Krishnendu Chakrabarty. 357-366 [doi]
• Using Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon DefectsWu-Tung Cheng, Manish Sharma, Artur Stelmach, Jakub Janicki, Preston McWithey, Gaurav Veda, Szczepan Urban, Jayant D'Souza. 367-376 [doi]
• 'Shifting-left' Zero Defect Scan Test Development to Launch Automotive PPM-ready ProductsRavi J. N, Stephen Traynor. 377-381 [doi]
• Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume ManufacturingSaghir A Shaikh, Brandon Brea, Gaurav Devrani, Muhammad Waheed, Lay Hoon Loh, Prakash Palanisamy, Jim Lee, Giyoung Yang. 382-386 [doi]
• Full Enablement of Very-Low Voltage Testing to Deliver Zero Defect Quality Automotive ProductsSrimaiyee Pentyala, Stephen Traynor. 387-391 [doi]
• Pseudo-Random Low Power Built In Self TestDale Meehl, Sameer Chillarige, Bharath Nandakumar, Carl Wisnesky, Krishna Chakravadhanula. 392-396 [doi]
• Ultra-Pure High-Resolution Waveform Generation Using Low-Cost Data Converters with DitheringEmmanuel Nti Darko, Saeid Karimpour, Ekaniyere Oko-Odion, Godfred Bonsu, Degang Chen 0001. 397-401 [doi]
• Functional Logic Diagnosis with Observation Points on Next-State VariablesIrith Pomeranz. 402-405 [doi]
• Early Testing of Memory Redundant Row ElementsLuc Romain, Roger Mah, Katarzyna Wojnowska, Albert Au, Lori Schramm. 406-409 [doi]
• Device-Aware Test for Threshold Voltage Shifting in FeFETChanghao Wang, Sicong Yuan, Nima Kolahimahmoudi, Hanzhi Xun, Nicolò Bellarmino, Danyang Chen, Chujun Yin, Mottaqiallah Taouil, Moritz Fieback, Xiuyan Li, Lin Wang 0111, Chaobo Li, Riccardo Cantoro, Said Hamdioui. 410-413 [doi]
• Scan Strategies for High Quality Latch Array TestingBin Du, Nehal Patel, Yerong Chen, Jeremy Chin, Katherine Tian. 414-417 [doi]
• Exploiting the correlation with traditional fault models to speed-up cell-aware fault simulationReza Khoshzaban, Iacopo Guglielminetti, Michelangelo Grosso, Matteo Sonza Reorda, Riccardo Cantoro. 418-421 [doi]
• Influence of Automated Test Equipment Drift on Process Capability StudiesAnand Venkatachalam, Ernst Aderholz, Matthias Sauer 0002, Simon Schweizer, Matthias Werner, Ilia Polian. 422-425 [doi]
• An SMT-Based Method for Identifying State-Holding Elements in Extracted NetlistsAric Fowler, Carl Sechen, Yiorgos Makris. 426-429 [doi]
• Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter ReflectionsNoeël Moeskops, Abdullah Aljuffri, Said Hamdioui, Mottaqiallah Taouil. 430-433 [doi]
• Improving Error Tolerance and Scalability in Pseudo-Boolean SAT-based Generic Side-Channel AnalysisShakil Ahmed, Dipali Jain, Kaveh Shamsi. 434-437 [doi]
• Test Pattern Aware Streaming Fabric-based Scan Test MethodologyKrishna Prasad Gnawali, Andrea Costa, Nathalie Etono, Denis Martin, Bala Tarun Nelapatla, Amit Purohit. 438-441 [doi]
• Embedded Trace: A Key Enabler for Silicon Lifecycle ManagementVivek Chickermane, Marcel Zak, Mat O'Donnell. 442-445 [doi]
• Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit AlignmentRiccardo Vettori, Alessia Galli. 446-449 [doi]
• CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data CorruptionXun Jiao, Sunny Yang, Suman Gumudavelli, Shreya Varshini, Abhinav Pandey, Abhinav Jauhri, Francesco Caggioni, Gautham Vunnam, Harish Dattatraya Dixit, Jason Liang, Philip Henzler, Sameeksha Gupta, Tyler Graf, Venkat Ramesh, Fan Fred Lin. 450-453 [doi]
• In-Field Testing using In-System Embedded Deterministic Test as a solution to alleviate Silent Data Corruption in AI designsVarun Sehgal, Subramanian Mahadevan, Ashrith S. Harith, Mohit Sharma, Saket Goyal, Nilanjan Mukherjee 0001. 454-457 [doi]
• High Reliability Delay-Based Weak FPGA PUF Using High-Resolution Stochastic Delay Measurement With Phase Locked LoopsKentaroh Katoh, Toru Nakura, Haruo Kobayashi 0001. 458-461 [doi]
• Graph Attention Networks Based Fault Prediction Framework for Functional Safety VerificationYutao Sun, Jiehua Huang, Xiangping Liao, Zhijun Wang, Liping Liang. 462-465 [doi]
• Why is Rigorous PCIe LTSSM Testing a Key to Robust and Reliable Systems?Sean Chen, Amarildo Garcia, Frank Chang, Joe Obedowski, Victor Castillo. 466-469 [doi]
• Minimal Supervision, Maximum Accuracy: TabPFN for Microcontroller Performance PredictionNicolò Bellarmino, Riccardo Cantoro, Martin Huch, Tobias Kilian, Annachiara Ruospo. 470-473 [doi]
• Secure and Efficient Sharing of On-Chip ResourcesJoel Åhlund, Markus Törmänen, Erik Larsson. 474-477 [doi]
• FAMOUS: Fault Attack Mitigation via Exploiting Invariances in Deep Neural NetworksJavad Bahrami, Parsa Nooralinejad, Hamed Pirsiavash, Naghmeh Karimi. 478-481 [doi]
• STARTS: Simulation Traits Assisted Random Test Selection for Multiprocessor VerificationLi Zhou, Menglong Lu, Li Luo, Jianfeng Zhang, Junbo Tie. 482-485 [doi]
• MUX-based Polymorphic Registers and FSMs to Protect Roots of Trust from Voltage Fault InjectionSourav Roy, Domenic Forte. 486-489 [doi]
• Teaching Llamas to Test: A Language-Based ApproachChristos Vasileiou, Yiorgos Makris. 490-493 [doi]
• Test and Calibration Methods for Process Variation of ReRAM-based Spiking Neural NetworksPo-Sheng Chiu, Chih-Yu Hsu, Chih-Tsun Huang, Jing-Jia Liou. 494-497 [doi]
• Early Reliability Estimation in Hardware Accelerators using Improved Colored Petri NetsErnesto Cristopher Villegas Castillo, Felipe Augusto da Silva, Josie E. Rodriguez Condia, Juan-David Guerrero-Balaguera, Michael Glaß. 498-501 [doi]
• Method for Diagnosing Clock Jitter Using FPGASeongkwan Lee, HyunTae Jeong, Cheolmin Park, Jun Yeon Won, Minho Kang, Jaemoo Choi. 502-505 [doi]
• Combined Array and ADC Structural Test for RRAM-based Multiply-and-Accumulate CircuitsEmmanouil Anastasios Serlis, Hanzhi Xun, Emmanouil Arapidis, Anteneh Gebregiorgis, Mottaqiallah Taouil, Said Hamdioui, Moritz Fieback. 506-509 [doi]
• Wafer Map Pattern Recognition for Multisite Probe with Synthetic Data Augmented TrainingChen He, Rebecca Chen, Patrick Goertz. 510-513 [doi]
• *Deepesh Sahoo, Eduardo Ortega, Peter Domanski, Farshad Firouzi, Krishnendu Chakrabarty. 514-517 [doi]
• *Dhruv Thapar, Arjun Chaudhuri, Kai Ni 0004, Krishnendu Chakrabarty. 518-521 [doi]
• Deep Learning-based IC MonitoringIresh M. Jayawardana, Krishna Dahal, Spyros Tragoudas, Khader S. Abdel-Hafez, Danushka Senarathna. 522-525 [doi]
• An On-Chip Sensor For Online Monitoring of HCI-Induced Aging In Integrated Analog CircuitsSaeid Karimpour, Emmanuel Nti Darko, Degang Chen 0001. 526-529 [doi]
• Test Bin Entitlement: Yield Outlier Detection using Die Area and LLM based Bin-GroupingRagad Al-Huq, Yuegui Zheng. 530-533 [doi]
• Experimental Comparison of Multiplexing Methods for 28 to 64 Gbps NRZ Test SignalsCao Wang, Shengbo Liu, Ming Cheng, Yindong Xiao, Xiaochun Li, David Keezer. 534-537 [doi]
• FPGA Synthesis of Arbitrary Jitter Injection for Multi-GHz Test SignalsShengbo Liu, Yindong Xiao, Cao Wang, Xiaochun Li, David Keezer. 538-541 [doi]
• Structural Testing on SLT Platform with HSAT IP & High-Speed I/O AccessJyotika Suri, Rakesh Kinger, Sridhar Nimmagadda, Henry Fei. 542-545 [doi]
• Thermal Management in System Level Test: Analysis of existing solutions and an introduction to advanced liquid cooled memory solutionsSridutt Tummalapalli, Srinath Reddy Yerakondappagari. 546-549 [doi]
• Embedded Trace: A Key Enabler for Silicon Lifecycle ManagementVivek Chickermane, Marcel Zak, Mat O'Donnell. 550-553 [doi]
• Hybrid Static Learning for ATPGJonathon E. Colburn, Peter Wohl, John A. Waicukauski, Yasunari Kanzawa. 554-557 [doi]
• FSWGEN: a Device-tree Specification driven System-Level Test workload generatorGabriele Filipponi. 558-559 [doi]
• A Benchmark Suite to Evaluate DNN's ResilienceCristiana Bolchini, Alberto Bosio, Luca Cassano, Antonio Miele, Salvatore Pappalardo, Dario Passariello, Annachiara Ruospo, Ernesto Sánchez 0001, Matteo Sonza Reorda, Vittorio Turco. 560-562 [doi]
• LAMBDA: LLM-Assisted Malicious Bug Detection and Analysis in Hardware DesignsSudipta Paria. 563-565 [doi]
• A Novel Tester-Based Approach for Functional Testing of Hardware TimersNicola Di Gruttola Giardino. 566-567 [doi]
• System-Level Test techniques for Automotive SoCsFrancesco Angione, Paolo Bernardi, Riccardo Cantoro. 568-577 [doi]
• Chiplet Interconnect Test and RepairPo-Yao Chuang, Cheng-Wen Wu, Erik Jan Marinissen. 578-587 [doi]
• Test Data Compaction Techniques with Improved Diagnostic Capabilities and Reduced Tester TimeJaidev Shenoy, Virendra Singh, Kelly Ockunzzi. 588-598 [doi]
• Leveraging UCIe Interface for Silicon Health & Reliabiilty of Chiplets in a 3D StackSandeep Kumar Goel, Ankita Patidar, Stanley John, Frank Lee 0004, Min-Jer Wang, Daniel F. J. Yang, Yervant Zorian, Manish Arora, Firooz Massoudi, Shaan Awasthi, Stelios Balalis, Velmurugan Pathervellaichamy, Bharath Shankaranarayanan, Narasimhalu Raju, Gurgen Harutyunyan, Grigor Tshagharyan, Vahagn Hovakimyan, Arman Karagyozyan, Alvina Manucharyan. 599-608 [doi]