Table of Contents

• Allocating Physically Aware Embedded Memory Test & Repair Processor using Floorplan Info at the RTL Design LevelVinay Kumar, Bhrugurajsinh Chudasama, Bin B. W. Wang, Manish Arora, Bharath Shankaranarayanan. 1-4 [doi]
• Predicting the Silent Data Error Prone Devices Using Machine LearningMohammad Ershad Shaik, Abhishek Kumar Mishra, Yonghyun Kim. 1-4 [doi]
• Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die PackagesPo-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen. 1-6 [doi]
• Compact Set of Functional Broadside Tests with Fault Detection on Primary OutputsIrith Pomeranz. 1-7 [doi]
• Machine Learning-Based Adaptive Outlier Detection for Underkill Reduction in Analog/RF IC TestingV. A. Niranjan, Deepika Neethirajan, Constantinos Xanthopoulos, D. Webster, Amit Nahar, Yiorgos Makris. 1-7 [doi]
• Architectural Radiation Hardening of CMOS Power Management Circuits through Bias TuningGauri Koli, Liam Nguyen, Jennifer Kitchen. 1-8 [doi]
• Expanding a Pool of Functional Test Sequences to Support Test CompactionIrith Pomeranz. 1-7 [doi]
• *Shao-Chun Hung, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty. 1-4 [doi]
• Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologiesFabio Pavanello, Elena Ioana Vatajelu, Alberto Bosio, Thomas Van Vaerenbergh, Peter Bienstman, Benoît Charbonnier, Alessio Carpegna, Stefano Di Carlo, Alessandro Savino. 1-10 [doi]
• Kernel Smoothing Technique Based on Multiple-Coordinate System for Screening Potential Failures in NAND Flash MemoryGooyoung Kim, Youngseon Moon, Jongmin Kim, JaeYong Jeong, Eun-Kyoung Kim, Sunghoi Hur. 1-7 [doi]
• ∗Arjun Chaudhuri, Ching-Yuan Chen, Jonti Talukdar, Krishnendu Chakrabarty. 1-6 [doi]
• Fully Deterministic Storage Based Logic Built-In Self-TestSubashini Gopalsamy, Irith Pomeranz. 1-7 [doi]
• A Novel LBIST Signature Computation Method for Automotive Microcontrollers using a Digital TwinDaniel Tille, Leon Klimasch, Sebastian Huhn 0001. 1-6 [doi]
• An Exploration of ATPG Methods for Redacted IP and Reconfigurable HardwareJackson Fugate, Greg Stitt, Naren Vikram Raj Masna, Aritra Dasgupta, Swarup Bhunia, Nij Dorairaj, David Kehlet. 1-7 [doi]
• Innovation Practices Track: Silicon Lifecycle Management Challenges and OpportunitiesFei Su, Xiankun Robert Jin, Nilanjan Mukherjee 0001, Yervant Zorian. 1 [doi]
• A Low Overhead Checksum Technique for Error Correction in Memristive Crossbar for Deep Learning ApplicationsSurendra Hemaram, Soyed Tuhin Ahmed, Mahta Mayahinia, Christopher Münch, Mehdi B. Tahoori. 1-7 [doi]
• Special Session: Security Verification & Testing for SR-Latch TRNGsJavad Bahrami, Mohammad Ebrahimabadi, Jean-Luc Danger, Sylvain Guilley, Naghmeh Karimi. 1-10 [doi]
• CAPEC: A Cellular Automata Guided FSM-based IP Authentication SchemeMridha Md Mashahedur Rahman, M. Sazadur Rahman, Rasheed Kibria, Mike Borza, Bandy Reddy, Adam Cron, Fahim Rahman, Mark M. Tehranipoor, Farimah Farahmandi. 1-8 [doi]
• Graph Neural Networks for Hardware Vulnerability Analysis - Can you Trust your GNN?Lilas Alrahis, Ozgur Sinanoglu. 1-4 [doi]
• IP Session on Chiplet: Design, Assembly, and TestBapi Vinnakota, Jaber Derakhshandeh, Eric Beyne, Erik Jan Marinissen, Sreejit Chakravarty. 1 [doi]
• Hybrid Binary Neural Networks: A Tutorial ReviewAhmet Enis Çetin, Hongyi Pan. 1-12 [doi]
• Pre and post silicon server platform transient performance using trans-inductor voltage regulatorJudy Amanor-Badu, Ritchie Rice, Azizi Shuma, Rishik Bazaz, Horthense Tamdem. 1-5 [doi]
• Gerabaldi: A Temporal Simulator for Probabilistic IC Degradation and Failure ProcessesIan Hill, André Ivanov. 1-7 [doi]
• An Efficient External Memory Test Solution: Case Study for HPC ApplicationKeqing Ouyang, Minqiang Peng, Yunnong Zhu, Kang Qi, Grigor Tshagharyan, Arun Kumar, Gurgen Harutyunyan, Isaac Wang. 1-4 [doi]
• Innovation Practices Track: VLSI Functional SafetyFei Su, Meirav Nitzan, Ankush Sethi, Vaibhav Kumar, Dan Alexandrescu. 1 [doi]
• Silent Data Errors: Sources, Detection, and ModelingAdit D. Singh, Sreejit Chakravarty, George Papadimitriou 0001, Dimitris Gizopoulos. 1-12 [doi]
• Diagnosis of Quantum Circuits in the NISQ EraYu-Min Li, Cheng-Yun Hsieh, Yen-Wei Li, James Chien-Mo Li. 1-7 [doi]
• Innovation Practices Track: Testability and Dependability of AI Hardware and Autonomous SystemsFei Su, Eric Zhang, Arjun Chaudhuri, Michael Paulitsch. 1 [doi]
• Vmin Prediction Using Nondestructive Stress TestChun Chen, Jeng-Yu Liao, James Chien-Mo Li, Harry H. Chen, Eric Jia-Wei Fang. 1-7 [doi]
• Overcoming Embedded Memory Test & Repair Challenges in the Gate-All-Around EraArtur Ghukasyan, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian. 1-4 [doi]
• Special Session: CAD for Hardware Security - Promising Directions for Automation of Security AssuranceSohrab Aftabjahani, Mark M. Tehranipoor, Farimah Farahmandi, Bulbul Ahmed, Ryan Kastner, Francesco Restuccia, Andres Meza, Kaki Ryan, Nicole Fern, Jasper Van Woudenberg, Rajesh Velegalati, Cees-Bart Breunesse, Cynthia Sturton, Calvin Deutschbein. 1-10 [doi]
• Refreshing the JTAG FamilyMichele Portolan, Martin Keim, Jeff Rearick, Heiko Ehrenberg. 1-7 [doi]
• Special Session: Approximation and Fault Resiliency of DNN AcceleratorsMohammad Hasan Ahmadilivani, Mario Barbareschi, Salvatore Barone, Alberto Bosio, Masoud Daneshtalab, Salvatore Della Torca, Gabriele Gavarini, Maksim Jenihhin, Jaan Raik, Annachiara Ruospo, Ernesto Sánchez 0001, Mahdi Taheri. 1-10 [doi]
• Innovation Practices Track: Innovation on Telemetry MonitoringFei Su, Marc Hunter, Chen He, Sashi Obilisetty. 1 [doi]
• Reliable Brain-inspired AI Accelerators using Classical and Emerging MemoriesMikail Yayla, Simon Thomann, Md Mazharul Islam, Ming-Liang Wei, Shu-Yin Ho, Ahmedullah Aziz, Chia-Lin Yang, Jian-Jia Chen, Hussam Amrouch. 1-10 [doi]
• Test Generation for Defect-Based Faults of Scan Flip-FlopsYu-Teng Nien, Chen-Hong Li, Pei-Yin Wu, Yung-Jheng Wang, Kai-Chiang Wu, Mango C.-T. Chao. 1-7 [doi]
• Thwarting Reverse Engineering Attacks through Keyless Logic ObfuscationLeon Li, Alex Orailoglu. 1-6 [doi]
• Design for testability (DFT) for RSFQ circuitsMingye Li, Yunkun Lin, Sandeep Gupta. 1-7 [doi]
• A guided debugger-based fault injection methodology for assessing functional test programsFrancesco Angione, Paolo Bernardi, Nicola Di Gruttola Giardino, Davide Appello, Claudia Bertani, Vincenzo Tancorre. 1-7 [doi]
• Targeted Custom High-Voltage Stress Patterns on Automotive DesignsSaidapet Ramesh, Kristofor Dickson, Akshay Jaiswal, Robert Marchese, Kiran Sunny Thota. 1-4 [doi]
• Auxiliary State Machine Controlled Autonomous Design Verification FrameworkGurumurti Kailaschandra Avhad, Shitin Sahu, Navaneeth Kumar. 1-5 [doi]
• Outlier Detection for Analog Tests Using Deep Learning TechniquesChin-Kuan Lin, Cheng-Che Lu, Shuo-Wen Chang, Ying-Hua Chu, Kai-Chiang Wu, Mango Chia-Tso Chao. 1-7 [doi]