Table of Contents

• Welcome Message ITC 2023Li-C. Wang, Jeff Rearick. [doi]
• A New Framework for RTL Test Points Insertion Facilitating a "Shift-Left DFT" StrategyHiroyuki Iwata, Yoichi Maeda, Jun Matsushima, Oussama Laouamri, Naveen Khanna, Jeff Mayer, Nilanjan Mukherjee. 1-10 [doi]
• A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT ImplementationAnshuman Chandra, Moiz Khan, Ankita Patidar, Fumiaki Takashima, Sandeep Kumar Goel, Bharath Shankaranarayanan, Vuong Nguyen, Vistrita Tyagi, Manish Arora. 11-20 [doi]
• New Algorithm for Fast and Accurate Linearity Testing of High-Resolution SAR ADCsAswin R. 21-29 [doi]
• Improving Angle of Arrival Estimation Accuracy for mm-Wave RadarsFerhat Can Ataman, Y. B. Chethan Kumar, Sandeep Rao, Sule Ozev. 30-36 [doi]
• OATT: Outlier Oriented Alternative Testing and Post-Manufacture Tuning of Mixed-Signal/RF Circuits and SystemsSuhasini Komarraju, Akhil Tammana, Chandramouli N. Amarnath, Abhijit Chatterjee. 37-46 [doi]
• Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital PredistortionKeno Sato, Takayuki Nakatani, Takashi Ishida 0003, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Daisuke Iimori, Misaki Takagi, Yujie Zhao, Shuhei Yamamoto, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi 0001. 47-55 [doi]
• Maximizing Stress Coverage by Novel DFT Techniques and Relaxed Timing ClosureArani Sinha, Glenn Colón-Bonet, Michael Fahy, Pankaj Pant, Haijing Mao, Akhilesh Shukla. 56-59 [doi]
• Novel Methodology to Optimize TAT and Resource Utilization for ATPG Simulations for Large SoCsSudhakar Kongala, Anuj Gupta, Yash Walia, Sahil Jain. 60-64 [doi]
• Global Control Signal Defect Diagnosis in Volume Production EnvironmentSzczepan Urban, Piotr Zimnowlodzki, Manish Sharma, Shraddha Bodhe, John Schulze, Abdullah Yassine, Adam Styblinski. 65-70 [doi]
• Method for Diagnosing Channel Damage Using FPGA TransceiverSeongkwan Lee, Jun Yeon Won, Cheolmin Park, Minho Kang, Jaemoo Choi. 71-76 [doi]
• Method for Adjusting Termination Resistance Using PMU in DC TestSeongkwan Lee, Minho Kang, Cheolmin Park, Jun Yeon Won, Jaemoo Choi. 77-81 [doi]
• Transitioning eMRAM from Pilot Project to Volume ProductionCyrille Dray, Khushal Gelda, Benoit Nadeau-Dostie, Wei Zou, Luc Romain, Jongsin Yun, Harshitha Kodali, Lori Schramm, Martin Keim. 82-86 [doi]
• Algorithmic Read Resistance Trim for Improving Yield and Reducing Test Time in MRAMDaehyun Chang, Youngdae Kim, Suksoo Pyo, Shin Hun, Daesop Lee, Sohee Hwang, Jaesik Choi, Siwoong Kim. 87-92 [doi]
• Machine-Learning Driven Sensor Data Analytics for Yield Enhancement of Wafer ProbingNadun Sinhabahu, Katherine Shu-Min Li, Sying-Jyan Wang, J. R. Wang, Matt Ho. 93-98 [doi]
• Domain-Specific Machine Learning Based Minimum Operating Voltage Prediction Using On-Chip Monitor DataYuxuan Yin, Rebecca Chen, Chen He, Peng Li. 99-104 [doi]
• Compaction of Functional Broadside Tests for Path Delay Faults Using Clusters of Propagation LinesIrith Pomeranz. 105-110 [doi]
• Robust Pattern Generation for Small Delay Faults Under Process VariationsHanieh Jafarzadeh, Florian Klemme, Jan Dennis Reimer, Zahra Paria Najafi-Haghi, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich. 111-116 [doi]
• Logic Test Vehicles for High Resolution Diagnosis of Systematic FEOL/MEOL Yield DetractorsYinxuan Lyu, Liangliang Yu, Pengju Li, Junlin Huang. 117-121 [doi]
• IEA-Plot: Conducting Wafer-Based Data Analytics Through ChatMatthew Dupree, Min-Jian Yang, Yueling Jenny Zeng, Li-C. Wang. 122-131 [doi]
• Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble LearningMakoto Eiki, Tomoki Nakamura, Masuo Kajiyama, Michiko Inoue, Takashi Sato, Michihiro Shintani. 132-140 [doi]
• Recognizing Wafer Map Patterns Using Semi-Supervised Contrastive Learning with Optimized Latent Representation Learning and Data AugmentationZihu Wang, Hanbin Hu, Chen He, Peng Li. 141-150 [doi]
• Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low TemperaturesFrancesco Lorenzelli, Asser Elsayed, Clement Godfrin, Alexander Grill, Stefan Kubicek, Ruoyu Li, Michele Stucchi, Danny Wan, Kristiaan De Greve, Erik Jan Marinissen, Georges G. E. Gielen. 151-158 [doi]
• GPU-Based Concurrent Static LearningHuaxiao Liang, Xiaoze Lin, Liyang Lai, Naixing Wang, Yu Huang, Fei Yang, Yuxin Yang. 159-165 [doi]
• Biochip-PUF: Physically Unclonable Function for Microfluidic BiochipsNavajit Singh Baban, Ajymurat Orozaliev, Yong-Ak Song, Urbi Chatterjee, Sankalp Bose, Sukanta Bhattacharjee, Ramesh Karri, Krishnendu Chakrabarty. 166-175 [doi]
• Understanding and Improving GPUs' Reliability Combining Beam Experiments with Fault SimulationFernando Fernandes dos Santos, Luigi Carro, Paolo Rech. 176-185 [doi]
• A Full-Stack Approach for Side-Channel Secure ML HardwareAnuj Dubey, Aydin Aysu. 186-195 [doi]
• Towards Robust Deep Neural Networks Against Design-Time and Run-Time FailuresYu Li, Qiang Xu. 196-205 [doi]
• High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test PatternsZhe-Jia Liang, Yu-Tsung Wu, Yun-Feng Yang, James Chien-Mo Li, Norman Chang, Akhilesh Kumar, Ying Shiun Li. 206-215 [doi]
• Scan Cell Segmentation Based on Reinforcement Learning for Power-Safe Testing of Monolithic 3D ICsShao-Chun Hung, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty. 216-225 [doi]
• Improving Productivity and Efficiency of SSD Manufacturing Self-Test Process by Learning-Based Proactive Defect PredictionYunfei Gu, Xingyu Wang, Zixiao Chen, Chentao Wu, Xinfei Guo, Jie Li, Minyi Guo, Song Wu, Rong Yuan, Taile Zhang, Yawen Zhang, Haoran Cai. 226-235 [doi]
• Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMsSicong Yuan, Z. Zhang, Moritz Fieback, Hanzhi Xun, Erik Jan Marinissen, Gouri Sankar Kar, Sidharth Rao, Sebastien Couet, M. Taouil, Said Hamdioui. 236-245 [doi]
• Device-Aware Test for Ion Depletion Defects in RRAMsHanzhi Xun, Sicong Yuan, Moritz Fieback, Hassen Aziza, Mottaqiallah Taouil, Said Hamdioui. 246-255 [doi]
• Analysis and Characterization of Defects in FeFETsDhruv Thapar, Simon Thomann, Arjun Chaudhuri, Hussam Amrouch, Krishnendu Chakrabarty. 256-265 [doi]
• Enhanced ML-Based Approach for Functional Safety Improvement in Automotive AMS CircuitsAyush Arunachalam, Sanjay Das, Monikka Rajan, Fei Su, Xiankun Jin, Suvadeep Banerjee, Arnab Raha, Suriyaprakash Natarajan, Kanad Basu. 266-275 [doi]
• Preventing Single-Event Double-Node Upsets by Engineering Change Order in Latch DesignsSam M.-H. Hsiao, Amy H.-Y. Tsai, Lowry P.-T. Wang, Aaron C.-W. Liang, Charles H.-P. Wen, Herming Chiueh. 276-285 [doi]
• Measuring Non-Redundant VIA Test-Coverage for Automotive Designs in Lower Process NodesSaidapet Ramesh, Rahul Kalyan, Jesse Yanez, Andreas Glowatz, Maija Ryynänen, Sergej Schwarz. 286-292 [doi]
• Diagnosis of Systematic Delay Failures Through Subset Relationship AnalysisBing-Han Hsieh, Yun-Sheng Liu, James Chien-Mo Li, Chris Nigh, Mason Chern, Gaurav Bhargava. 293-302 [doi]
• Predicting the Resolution of Scan DiagnosisManoj Devendhiran, Jakub Janicki, Szczepan Urban, Manish Sharma, Jayant D'Souza. 303-309 [doi]
• Predictor BIST: An "All-in-One" Optical Test Solution for CMOS Image SensorsJ. Lefevre, P. Debaud, P. Girard, Arnaud Virazel. 310-319 [doi]
• ARC-FSM-G: Automatic Security Rule Checking for Finite State Machine at the Netlist AbstractionRasheed Kibria, Farimah Farahmandi, Mark M. Tehranipoor. 320-329 [doi]
• Laser Fault Injection Vulnerability Assessment and Mitigation with Case Study on PG-TVD Logic CellsRyan Holzhausen, Tasnuva Farheen, Morgan-Thomas, Nima Maghari, Domenic Forte. 330-339 [doi]
• Simply-Track-and-Refresh: Efficient and Scalable Rowhammer MitigationEduardo Ortega, Tyler K. Bletsch, Biresh Kumar Joardar, Jonti Talukdar, Woohyun Paik, Krishnendu Chakrabarty. 340-349 [doi]
• Low cost production scan chain test for compression based designsBharath Nandakumar, Sameer Chillarige. 350-356 [doi]
• Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern InformationChing-Min Liu, Chia-Heng Yen, Shu-Wen Lee, Kai-Chiang Wu, Mango Chia-Tso Chao. 357-366 [doi]
• Enabling In-Field Parametric Testing for RISC-V CoresSeyedeh Maryam Ghasemi, Sergej Meschkov, Jonas Krautter, Dennis R. E. Gnad, Mehdi B. Tahoori. 367-376 [doi]
• Estimating the Failures and Silent Errors Rates of CPUs Across ISAs and MicroarchitecturesDimitris Gizopoulos, George Papadimitriou 0001, Odysseas Chatzopoulos. 377-382 [doi]
• Utilizing ECC Analytics to Improve Memory Lifecycle ManagementCostas Argyrides, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian. 383-387 [doi]
• SLM Subsystem for Automotive SoC: Case Study on Path Margin MonitorKranthi Kandula, Ramalingam Kolisetti, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian. 388-392 [doi]