Abstract is missing.
- Cross-Correlation Approach to Detecting Issue Test Sites in Massive Parallel TestingPraise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi 0001, Degang Chen 0001. 1-6 [doi]
- Model-Based Analysis of Single-Event Upset (SEU) Vulnerability of 6T SRAM Using FinFET TechnologiesSemiu A. Olowogemo, Hao Qiu, Bor-Tyng Lin, William H. Robinson, Daniel B. Limbrick. 1-4 [doi]
- Neutron Irradiation Testing and Analysis of a Fault-Tolerant RISC-V System-on-ChipDouglas A. dos Santos, André Martins Pio de Mattos, Lucas M. Luza, Carlo Cazzaniga, Maria Kastriotou, Douglas R. Melo, Luigi Dilillo. 1-6 [doi]
- Operational Age Estimation of ICs using Gaussian Process RegressionAnmol Singh Narwariya, Pabitra Das, Saqib Khursheed, Amit Acharyya. 1-5 [doi]
- Is RISC-V ready for Space? A Security PerspectiveLuca Cassano, Stefano Di Mascio, Alessandro Palumbo, Alessandra Menicucci, Gianluca Furano, Giuseppe Bianchi 0001, Marco Ottavi. 1-6 [doi]
- Evaluation of Hiding-based Countermeasures against Deep Learning Side Channel Attacks with Pre-trained NetworksKonstantinos Nomikos, Athanasios Papadimitriou, Mihalis Psarakis, Aggelos Pikrakis, Vincent Beroulle. 1-6 [doi]
- Storage-Based Logic Built-In Self-Test with Variable-Length Test DataIrith Pomeranz. 1-6 [doi]
- Aging Effects On Clock Gated Memory Phase PathsAmlan Ghosh, Saroj Satapathy, Jaydeep P. Kulkarni, Prashant D. Joshi. 1-5 [doi]
- Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input VoltagesJianan Wen, Andrea Baroni, Eduardo Perez, Markus Ulbricht 0002, Christian Wenger, Milos Krstic. 1-6 [doi]
- Efficient Loop Abort Fault Attacks on Supersingular Isogeny based Key Exchange (SIKE)Piyush Beegala, Debapriya Basu Roy, Prasanna Ravi, Shivam Bhasin, Anupam Chattopadhyay, Debdeep Mukhopadhyay. 1-6 [doi]
- Integral Sampler and Polynomial Multiplication Architecture for Lattice-based CryptographyAntian Wang, Weihang Tan, Keshab K. Parhi, Yingjie Lao. 1-6 [doi]
- X-Ray Fault Injection: Reviewing Defensive Approaches from a Security PerspectiveNasr-Eddine Ouldei Tebina, Nacer-Eddine Zergainoh, Paolo Maistri. 1-4 [doi]
- Evaluation of the Effects of SEUs on Configuration Memories in FPGA Implemented QC-LDPC DecodersZhen Gao 0005, Yinghao Cheng, Pedro Reviriego. 1-6 [doi]
- Thread-level Parallelism in Fault Simulation of Deep Neural Networks on Multi-Processor SystemsMasoomeh Karami, Mohammad Hashem Haghbayan, Masoumeh Ebrahimi, Antonio Miele, Juha Plosila. 1-4 [doi]
- A Polarity-Driven Radiation-Hardened Latch design for Single Event Upset ToleranceShanshan Liu, Jing Guo 0004, Xiaochen Tang, Pedro Reviriego, Fabrizio Lombardi. 1-6 [doi]
- SET Hardened Derivatives of QDI Buffer TemplateZaheer Tabassam, Andreas Steininger. 1-6 [doi]
- Improving DNN Fault Tolerance in Semantic Segmentation ApplicationsStéphane Burel, Adrian Evans, Lorena Anghel. 1-6 [doi]
- Selective Hardening of CNNs based on Layer Vulnerability EstimationCristiana Bolchini, Luca Cassano, Antonio Miele, Alessandro Nazzari. 1-6 [doi]
- Understanding time-varying vulnerability accross GPU Program LifetimeHao Qiu, Semiu A. Olowogemo, Bor-Tyng Lin, William H. Robinson, Daniel B. Limbrick. 1-6 [doi]
- RADPlace-MS: A Timing-Driven Placer and Optimiser for ASICs Radiation HardeningChristos Georgakidis, Stavros Simoglou, Christos P. Sotiriou. 1-6 [doi]
- Analysis of Proton-induced Single Event Effect in the On-Chip Memory of Embedded ProcessCorrado De Sio, Sarah Azimi, Luca Sterpone, David Merodio Codinachs. 1-6 [doi]
- Toward the hardening of real-time operating systemsAlberto Bosio, Stefano Di Carlo, Maurizio Rebaudengo, Alessandro Savino. 1-6 [doi]
- Preventing Soft Errors and Hardware Trojans in RISC-V CoresEdian B. Annink, Gerard K. Rauwerda, Edwin A. Hakkennes, Alessandra Menicucci, Stefano Di Mascio, Gianluca Furano, Marco Ottavi. 1-6 [doi]
- CRLock: A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer LevelMasayoshi Yoshimura, Atsuya Tsujikawa, Hiroshi Yamazaki, Toshinori Hosokawa. 1-6 [doi]
- INTERPLAY: An Intelligent Model for Predicting Performance Degradation due to Multi-cache Way-disablingPanagiota Nikolaou, Yiannakis Sazeides, Maria K. Michael. 1-7 [doi]
- Study and Comparison of QDI Pipeline Components' Sensitivity to Permanent FaultsRaghda El Shehaby, Andreas Steininger. 1-6 [doi]
- MetaFS: Model-driven Fault Simulation FrameworkEndri Kaja, Nicolas Gerlin, Monideep Bora, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker. 1-4 [doi]
- HPMA-NTRU: High-Performance Polynomial Multiplication Accelerator for NTRUPengzhou He, Yazheng Tu, Ayesha Khalid, Máire O'Neill, Jiafeng Xie. 1-6 [doi]
- Image Degradation due to Interacting Adjacent Hot PixelsGlenn H. Chapman, Klinsmann J. Coelho Silva Meneses, Israel Koren, Zahava Koren. 1-6 [doi]
- Online scheduling of concurrent Memory BISTs execution at Real-Time Operating-System levelFrancesco Angione, Paolo Bernardi, Gabriele Filipponi, Claudia Tempesta, Matteo Sonza Reorda, Davide Appello, Vincenzo Tancorre, Roberto Ugioli. 1-6 [doi]