Table of Contents

• Reliability Challenges for Advanced PackagingChristopher Bailey. 1-4 [doi]
• Revisiting DRAM Read Disturbance: Identifying Inconsistencies Between Experimental Characterization and Device-Level StudiesHaocong Luo, Ismail Emir Yüksel, Ataberk Olgun, A. Giray Yaglikçi, Onur Mutlu. 1-8 [doi]
• Test Methodology for Detecting Defect-Based Hold-Time FaultsCheng-Hsiang Tsai, Yu-Teng Nien, Guan-You Chen, Mango Chia-Tso Chao. 1-7 [doi]
• Timing-Verification Test Generation Targeting Small Delay DefectsJiezhong Wu, Nilanjan Mukherjee 0001, Irith Pomeranz, Kun-Han Tsai, Janusz Rajski. 1-7 [doi]
• Chip Aging and Double Transition FaultsIrith Pomeranz. 1-7 [doi]
• Electromigration Reliability Analysis of SRAM-based Register Files in GPUs and AI AcceleratorsMahta Mayahinia, Mehdi Baradaran Tahoori. 1-4 [doi]
• Designing Radiation-Hardened D Flip-Flop with Reduced Latency and Area Using Filtering BufferNelson M.-C. Wu, Lowry P.-T. Wang, Chia-Wei Liang, Charles H.-P. Wen, Herming Chiueh. 1-7 [doi]
• SPRING: Systematic Profiling of Randomly Interconnected Neural Networks Generated by HLSRui Shi, Seda Ogrenci. 1-5 [doi]
• LLM-IFT: LLM-Powered Information Flow Tracking for Secure HardwareNowfel Mashnoor, Mohammad Akyash, Hadi Mardani Kamali, Kimia Zamiri Azar. 1-5 [doi]
• Innovation Practices Track: Industry RAS/SDC Innovative Practices - from Silicon to Mega FleetsFei Su, Yogesh Varma, John Holm, Drew Walton. 1 [doi]
• Garblet: Multi-party Computation for Protecting Chiplet-based SystemsMohammad Hashemi, Shahin Tajik, Fatemeh Ganji. 1-7 [doi]
• Artificial Bee Colony Optimization to Accelerate High-Speed Serial I/O Tx EqualizationCesar A. Sánchez-Martínez, Paulo Lopez-Meyer, Andres Viveros-Wacher. 1-5 [doi]
• Opportunities for Built-In Self-Test Within Emerging mm-Wave Phased-Array and MIMO ArchitecturesNegar Reiskarimian. 1-5 [doi]
• A Multi-Step Algorithm to Increase Measurement Accuracy of mm-Wave BIST Using Periodic StructuresNoah Rajbharti, Esteban Chacon, Muslum Emir Avci, Jennifer Kitchen, Sule Ozev. 1-5 [doi]
• Hardware Security and Test for AMS CircuitsArjun Chaudhuri. 1 [doi]
• Low-Power Voltage Reference: Review & ProgressAbhishek Pullela, Ashfakh Huluvallay, Arpan Jain, Zia Abbas, Inhee Lee 0001. 1-5 [doi]
• Data-Efficient Prediction of Minimum Operating Voltage via Inter- and Intra-Wafer Variation AlignmentYuxuan Yin, Rebecca Chen, Chen He, Peng Li 0001. 1-7 [doi]
• DC Stimulus Electrical Calibration of MEMS AccelerometersIshaan Bassi, Sule Ozev. 1-7 [doi]
• Fine-Grained Steepening of the Fault Coverage Curve of a Pool of Functional Test SequencesIrith Pomeranz. 1-7 [doi]
• Revisiting Microelectronics Resilience and Reliability in the Era of AIArjun Chaudhuri, Bonita Bhaskaran. 1 [doi]
• From Signals to Features to Insights: Multi-Level Novelty Detection for Fast Scientific DiscoveryDevashri Naik, Nastaran Darabi, Sina Tayebati, Dinithi Jayasuriya, Shamma Nasrin, Danush Shekar, Corrinne Mills, Benjamin Parpillon, Farah Fahim, Mark S. Neubauer, Amit Ranjan Trivedi. 1-4 [doi]
• High-Accuracy, Cost-Effective Built-In Self-Test Approach for High-Resolution Data ConvertersEmmanuel Nti Darko, Saeid Karimpour, Degang Chen 0001. 1-7 [doi]
• Special Session: Bringing Symbolic Execution to the Security Verification of Hardware DesignsKaki Ryan, Cynthia Sturton. 1-4 [doi]
• Enhancing Metrology to E-test Correlation Model Accuracy through Process Expertise IntegrationChing-Yi Chang, Matthew Nigh, John M. Carulli, Yiorgos Makris. 1-7 [doi]
• Special Session: ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security VerificationDipayan Saha, Hasan Al Shaikh, Shams Tarek, Farimah Farahmandi. 1-5 [doi]
• OpenAssert: Towards Secure Assertion Generation using Large Language ModelsAnand Menon, Samit Shahnawaz Miftah, Amisha Srivastava, Shamik Kundu, Shovik Kundu, Arnab Raha, Suvadeep Banerjee, Deepak Mathaikutty, Kanad Basu. 1-5 [doi]
• Innovation Practices Track: Frontiers in Diagnosis and DebugSuriyaprakash Natarajan, Saghir A. Shaikh, Wu-Tung Cheng, Sankaran Menon. 1 [doi]
• ChipMnd: LLMs for Agile Chip DesignFarshad Firouzi, David Z. Pan, Jiaqi Gu 0002, Bahar J. Farahani, Jayeeta Chaudhuri, Ziang Yin, Pingchuan Ma, Peter Domanski, Krishnendu Chakrabarty. 1-10 [doi]
• Silent Data Corruption: Advancing Detection, Diagnosis, and Mitigation StrategiesPeter Domanski, Mukarram Ali Faridi, Gabriel Kaunang, Wilson Pradeep, Adit D. Singh, Muhammad Alfian Amrizal, Yanjing Li, Farshad Firouzi, Krishnendu Chakrabarty. 1-11 [doi]
• MOSAIC: Collaborative Compute-in-Memory µArrays for Flexible and Scalable Deep LearningAmit Ranjan Trivedi, Shamma Nasrin, Priyesh Shukla, Nastaran Darabi, Divake Kumar, Dinithi Jayasuriya, Nethmi Jayasinghe. 1-4 [doi]
• Challenge Selection for Salvaging Faulty APUFsYeqi Wei, Wenjing Rao, Natasha Devroye. 1-7 [doi]
• AI for Test : (Innovation Practices Track)Arjun Chaudhuri, Soyed Tuhin Ahmed. 1 [doi]
• CHEF: CHaracterizing Elusive Logic Circuit FailuresRuben Purdy, Chris Nigh, Wei Li, R. D. Shawn Blanton. 1-7 [doi]
• SCAPEgoat: Side-channel Analysis LibraryDev Mehta, Trey Marcantino, Mohammad Hashemi, Sam Karkache, Dillibabu Shanmugam, Patrick Schaumont, Fatemeh Ganji. 1-7 [doi]
• Reliable Board-Level Degradation Prediction with Monotonic Segmented Regression under Noisy MeasurementYuxuan Yin, Rebecca Chen, Varun Thukral, Chen He, Peng Li 0001. 1-7 [doi]
• Fault Modeling and Testing of ReRAM-based CAM ArrayHaneen G. Hezayyin, Mahta Mayahinia, Mehdi Baradaran Tahoori. 1-7 [doi]
• Test Complexity in the Semiconductor LandscapeSuma Ayyagari. 1-5 [doi]
• Special Session: Trustworthy Hardware-AI at the CloudFrancesco Angione, Paolo Bernardi, Alberto Bosio, Harish Dattatraya Dixit, Salvatore Pappalardo, Annachiara Ruospo, Ernesto Sánchez 0001, Arani Sinha, Vittorio Turco. 1-11 [doi]
• HighTPI: A Hierarchical Graph Based Intelligent Method for Test Point InsertionZhiteng Chao, Bin Sun, Hongqin Lyu, Ge Yu, Minjun Wang, Wenxing Li, Zizhen Liu, Jianan Mu, Shengwen Liang, Jing Ye 0001, Xiaowei Li, Huawei Li. 1-7 [doi]
• Special Session: Security Verification of Microelectronic Systems with Integrated AI Accelerators: Scope, Practice, and ChallengesKazi Mejbaul Islam, Tambiara Tabassum, Dipal Halder, Sandip Ray. 1-4 [doi]
• From Design to Inspection: Can Inspection-aware Design Enhance Reliability in Advanced Packaging?Katayoon Yahyaei, M. Shafkat M. Khan, Navid Asadizanjani. 1-5 [doi]
• Multi-core Vmin and Worst-core Vmin Prediction using SOMACJeng-Yu Liao, Li Yang Wang, James Chien-Mo Li, Harry H. Chen. 1-7 [doi]
• CBM-TI: Code-Based Masking against Glitches by Hybridization with Threshold ImplementationHasin Ishraq Reefat, Hossein Pourmehrani, Wei Cheng 0003, Claude Carlet, Abderrahman Daif, Cédric Tavernier, Sylvain Guilley, Naghmeh Karimi. 1-11 [doi]
• Periodic Non-Destructive Memory BIST for Automotive ApplicationsWei Zou, Artur Pogiel, Albert Au, Martin Keim. 1-7 [doi]
• Defect Severity Analysis for Analog Circuits Using Zoom Search and Hierarchical Fault SimulationMehmet Onder, Lakshmanan Balasubramanian, Rubin A. Parekhji, Suriyaprakash Natarajan, Sule Ozev. 1-7 [doi]
• Machine-learning based Blind Digital Calibration of Time-Interleaved ADCSumukh Prashant Bhanushali, Shamma Nasrin, Debnath Maiti, Arindam Sanyal. 1-5 [doi]
• CED-HDC: Lightweight Concurrent Error Detection for Reliable Hyperdimensional ComputingMahboobe Sadeghipour Roodsari, Vincent Meyers, Mehdi B. Tahoori. 1-7 [doi]
• Machine Learning Based Calibration Techniques for ADCs: An OverviewTuan Quang Pham, Sai Sanjeet, Bibhu Datta Sahoo 0002. 1-5 [doi]
• Gradient Attention Map Based Verification of Deep Convolutional Neural Networks with Application to X-ray Image DatasetsOmid Halimi Milani, Amanda Nikho, Lauren Mills, Marouane Tliba, Ahmet Enis Çetin, Mohammed H. Elnagar. 1-5 [doi]
• Gate Leakage Current Integration-Based Dielectric Breakdown Monitor in a 12nm FinFET ProcessMateo Rendón, Ian Hill, André Ivanov. 1-7 [doi]
• SALTY: Explainable Artificial Intelligence Guided Structural Analysis for Hardware Trojan DetectionTanzim Mahfuz, Pravin Gaikwad, Tasneem Suha, Swarup Bhunia, Prabuddha Chakraborty. 1-7 [doi]
• Test, Debug, and Repair for Chiplet-Based DesignsAnshuman Chandra, Esteban Garita-Rodríguez, Pradipta Ghosh. 1 [doi]
• *Partho Bhoumik, Christopher Bailey, Krishnendu Chakrabarty. 1-7 [doi]
• GLLaMoR: Graph-based Logic Locking by Large Language Models for Enhanced RobustnessAkashdeep Saha, Prithwish Basu Roy, Johann Knechtel, Ramesh Karri, Ozgur Sinanoglu, Lilas Alrahis. 1-5 [doi]
• Security Verification and Secure Testing SolutionsSohrab Aftabjahani, Wilson Pradeep. 1 [doi]
• BugWhisperer: Fine-Tuning LLMs for SoC Hardware Vulnerability DetectionShams Tarek, Dipayan Saha, Sujan Kumar Saha, Farimah Farahmandi. 1-5 [doi]
• ML-based Adaptive Wafer Sort to Preserve Diagnostic InformationYun-Sheng Liu, Min-Hsin Liu, James Chien-Mo Li. 1-7 [doi]
• APT: Optimal Tree for Diagnosis SimulationWu-Tung Cheng. 1-7 [doi]
• MicroFI: TensorFlow Lite based Fault Injection Framework for MicrocontrollersLeonardo Alexandrino De Melo, Rodrigo Possamai Bastos, Alberto Bosio. 1-7 [doi]
• Characterization and All-Region Virtual-Source Modeling of 40 nm GaN HEMT Technology for High Frequency IC DesignKexin Li, Armagan Dascurcu, Hari Vemuri, Harish Krishnaswamy. 1-5 [doi]
• CLIP: A Structural Approach to Cut Points Matching for Logic Equivalence CheckingDinesh Reddy Ankireddy, Sudipta Paria, Aritra Dasgupta 0002, Sandip Ray, Swarup Bhunia. 1-7 [doi]
• Towards Automated Verification of IP and COTS: Leveraging LLMs in Pre- and Post-Silicon StagesSudipta Paria, Aritra Dasgupta 0002, Swarup Bhunia. 1-5 [doi]