Table of Contents

• Wafer Map Defect Classification Based on the Fusion of Pattern and Pixel InformationYiwen Liao, Raphaël Latty, Paul R. Genssler, Hussam Amrouch, Bin Yang. 1-9 [doi]
• Modeling Challenge Covariances and Design Dependency for Efficient Attacks on Strong PUFsHongfei Wang, Wei Liu, Hai Jin, Yu Chen, Wenjie Cai. 1-10 [doi]
• DIST: Deterministic In-System Test with X-maskingGrzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak. 20-27 [doi]
• Reliability Study of 14 nm Scan Chains and Its Application to Hardware SecurityFranco Stellari, Peilin Song. 28-35 [doi]
• Neural Fault Analysis for SAT-based ATPGJunhua Huang, Hui-Ling Zhen, Naixing Wang, Hui Mao, Mingxuan Yuan, Yu Huang. 36-45 [doi]
• TAMED: Transitional Approaches for LFI Resilient State Machine EncodingMuhtadi Choudhury, Minyan Gao, Shahin Tajik, Domenic Forte. 46-55 [doi]
• Configurable BISR Chain For Fast Repair Data LoadingWei Zou, Benoit Nadeau-Dostie. 56-62 [doi]
• A Practical Online Error Detection Method for Functional Safety Using Three-Site ImplicationsKazuya Loki, Yasuyuki Kai, Kohei Miyase, Seiji Kajihara. 63-72 [doi]
• Transient Fault Pruning for Effective Candidate Reduction in Functional DebuggingDun-An Yang, Jing-Jia Liou, Harry H. Chen. 73-81 [doi]
• Scan-Based Test Chip Design with XOR-based C-testable Functional BlocksYan-Fu Chen, Duo-Yao Kang, Kuen-Jong Lee. 82-91 [doi]
• Fault Modeling and Testing of Memristor-Based Spiking Neural NetworksKuan-Wei Hou, Hsueh-Hung Cheng, Chi Tung, Cheng-Wen Wu, Juin-Ming Lu. 92-99 [doi]
• RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield ImprovementXiaopeng Zhang 0007, Shoubo Hu, Zhitang Chen, Shengyu Zhu 0001, Evangeline F. Y. Young, Pengyun Li, Cheng Chen, Yu Huang, Jianye Hao. 100-107 [doi]
• Compression-Aware ATPGXing Wang, Zezhong Wang 0006, Naixing Wang, Weiwei Zhang, Yu Huang. 108-117 [doi]
• Fault Diagnosis for Resistive Random-Access Memory and Monolithic Inter-tier Vias in Monolithic 3D IntegrationShao-Chun Hung, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty. 118-127 [doi]
• Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65nm CMOS TechnologiesSam M.-H. Hsiao, Lowry P.-T. Wang, Aaron C.-W. Liang, Charles H.-P. Wen. 128-136 [doi]
• Just-Enough Stress Test for Infant-Mortality Screening Using Speed BinningChen-Lin Tsai, Shi-Yu Huang. 137-144 [doi]
• Automatic Structural Test Generation for Analog Circuits using Neural TwinsJonti Talukdar, Arjun Chaudhuri, Mayukh Bhattacharya, Krishnendu Chakrabarty. 145-154 [doi]
• ADWIL: A Zero-Overhead Analog Device Watermarking Using Inherent IP FeaturesUpoma Das, Md Rafid Muttaki, Mark M. Tehranipoor, Farimah Farahmandi. 155-164 [doi]
• RTL-FSMx: Fast and Accurate Finite State Machine Extraction at the RTL for Security ApplicationsRasheed Kibria, M. Sazadur Rahman, Farimah Farahmandi, Mark Tehranipoor. 165-174 [doi]
• Diagnosing Double Faulty Chains through Failing Bit SeparationCheng-Sian Kuo, Bing-Han Hsieh, James Chien-Mo Li, Chris Nigh, Gaurav Bhargava, Mason Chern. 175-184 [doi]
• Efficient and Robust Resistive Open Defect Detection Based on Unsupervised Deep LearningYiwen Liao, Zahra Paria Najafi-Haghi, Hans-Joachim Wunderlich, Bin Yang. 185-193 [doi]
• DeepTPI: Test Point Insertion with Deep Reinforcement LearningZhengyuan Shi, Min Li, Sadaf Khan, Liuzheng Wang, Naixing Wang, Yu Huang, Qiang Xu 0001. 194-203 [doi]
• PPA Optimization of Test Points in Automotive DesignsBrian Foutz, Sarthak Singhal, Prateek Kumar Rai, Krishna Chakravadhanula, Vivek Chickermane, Bharath Nandakumar, Sameer Chillarige, Christos Papameletis, Satish Ravichandran. 204-212 [doi]
• ML-Assisted VminBinning with Multiple Guard Bands for Low Power ConsumptionWei-Chen Lin, Chun Chen, Chao-Ho Hsieh, James Chien-Mo Li, Eric Jia-Wei Fang, Sung S.-Y. Hsueh. 213-218 [doi]
• Reusing IEEE 1687-Compatible Instruments and Sub-Networks over a System BusFarrokh Ghani Zadegan, Zilin Zhang, Kim Petersén, Erik Larsson. 219-228 [doi]
• Unsupervised Learning-based Early Anomaly Detection in AMS Circuits of Automotive SoCsAyush Arunachalam, Athulya Kizhakkayil, Shamik Kundu, Arnab Raha, Suvadeep Banerjee, Robert Jin, Fei Su, Kanad Basu. 229-238 [doi]
• Compact Functional Test Generation for Memristive Deep Learning Implementations using Approximate Gradient RankingSoyed Tuhin Ahmed, Mehdi B. Tahoori. 239-248 [doi]
• Multi-die Parallel Test Fabric for Scalability and Pattern ReusabilityArani Sinha, Yonsang Cho, Jon Easter, Meizel V. Leiva Rojas. 249-257 [doi]
• A Path Selection Flow for Functional Path Ring Oscillators using Physical Design DataTobias Kilian, Markus Hanel, Daniel Tille, Martin Huch, Ulf Schlichtmann. 258-267 [doi]
• ML-Assisted Bug Emulation Experiments for Post-Silicon Multi-Debug of AMS CircuitsJun-Yang Lei, Abhijit Chatterjee. 268-277 [doi]
• A Multi-level Approach to Evaluate the Impact of GPU Permanent Faults on CNN's ReliabilityJosie E. Rodriguez Condia, Juan-David Guerrero-Balaguera, Fernando F. Dos Santos, Matteo Sonza Reorda, Paolo Rech. 278-287 [doi]
• Language Driven Analytics for Failure Pattern Feedforward and FeedbackMin-Jian Yang, Yueling Zeng, Li-C. Wang. 288-297 [doi]
• DEFCON: Defect Acceleration through Content OptimizationSuriyaprakash Natarajan, Abhijit Sathaye, Chaitali Oak, Nipun Chaplot, Suvadeep Banerjee. 298-304 [doi]
• Test Generation for an Iterative Design Flow with RTL ChangesJerin Joe, Nilanjan Mukherjee 0001, Irith Pomeranz, Janusz Rajski. 305-313 [doi]
• PEPR: Pseudo-Exhaustive Physically-Aware Region TestingWei Li, Chris Nigh, Danielle Duvalsaint, Subhasish Mitra, Ronald D. Blanton. 314-323 [doi]
• Error Model (EM) - A New Way of Doing Fault SimulationNirmal R. Saxena, Atieh Lotfi. 324-333 [doi]
• Comprehensive Power-Aware ATPG Methodology for Complex Low-Power DesignsKhader S. Abdel-Hafez, Michael Dsouza, Likith Kumar Manchukonda, Elddie Tsai, Karthikeyan Natarajan, Ting-Pu Tai, Wenhao Hsueh, Smith Lai. 334-339 [doi]
• Scaling physically aware logic diagnosis to complex high volume 7nm server processorsBharath Nandakumar, Madhur Maheshwari, Sameer Chillarige, Robert Redburn, Jeff Zimmerman, Nicholai L'Esperance, Edward Dziarcak. 340-347 [doi]
• Using Custom Fault Models to Improve Understanding of Silicon FailuresSubhadip Kundu, Gaurav Bhargava, Lesly Endrinal, Lavakumar Ranganathan. 348-354 [doi]
• An innovative Strategy to Quickly Grade Functional Test ProgramsFrancesco Angione, Paolo Bernardi, A. Calabrese, L. Cardone, A. Niccoletti, Davide Piumatti, Stefano Quer, Davide Appello, Vincenzo Tancorre, Roberto Ugioli. 355-364 [doi]
• Probeless DfT Scheme for Testing 20k I/Os of an Automotive Micro-LED Headlamp Driver ICHans Martin von Staudt, Luai Tarek Elnawawy, Sarah Wang, Larry Ping, Jung-Woo Choi. 365-371 [doi]
• Understanding Vmin Failures for Improved Testing of Timing MarginalitiesAdit D. Singh. 372-381 [doi]
• IEEE P1687.1: Extending the Network Boundaries for TestMichael Laisne, Alfred L. Crouch, Michele Portolan, Martin Keim, Hans Martin von Staudt, Bradford G. Van Treuren, Jeff Rearick, Songlin Zuo. 382-390 [doi]
• Fine-Grained Built-In Self-Repair Techniques for NAND Flash MemoriesShyue-Kung Lu, Shi-Chun Tseng, Kohei Miyase. 391-399 [doi]
• Accelerating RRAM Testing with a Low-cost Computation-in-Memory based DFTAbhairaj Singh, Moritz Fieback, Rajendra Bishnoi, Filip Bradaric, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui. 400-409 [doi]
• New R&R Methodology in Semiconductor Manufacturing Electrical TestingLorella Bordogna, Fabio Brembilla, Alberto Pagani, Marco Spinetta. 410-419 [doi]
• Industry Evaluation of Reversible Scan Chain DiagnosisSoumya Mittal, Szczepan Urban, Kun Young Chung, Jakub Janicki, Wu-Tung Cheng, Martin Parley, Manish Sharma, Shaun Nicholson. 420-426 [doi]
• Defect-Directed Stress Testing Based on Inline Inspection ResultsChen He, Paul Grosch, Onder Anilturk, Joyce Witowski, Carl Ford, Rahul Kalyan, John C. Robinson, David W. Price, Jay Rathert, Barry Saville, Dave Lee. 427-435 [doi]
• Application of Sampling in Industrial Analog Defect SimulationMayukh Bhattacharya, Beatrice Solignac, Michael Dürr. 436-445 [doi]
• Low Capture Power At-Speed Test with Local Hot Spot Analysis to Reduce Over-TestAnkush Srivastava, Jais Abraham. 446-455 [doi]
• Challenges for High Volume Testing of Embedded IO Interfaces in Disaggregated Microprocessor ProductsEsteban Garita-Rodríguez, Renato Rimolo-Donadio, Rafael Zamora-Salazar. 456-464 [doi]
• Achieving Automotive Safety Requirements through Functional In-Field Self-Test for Deep Learning AcceleratorsTakumi Uezono, Yi He 0010, Yanjing Li. 465-473 [doi]
• Transforming an $n$-Detection Test Set into a Test Set for a Variety of Fault ModelsIrith Pomeranz. 474-478 [doi]
• Hardware Root of Trust for SSN-basedDFT EcosystemsJanusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak. 479-483 [doi]
• A Comprehensive Learning-Based Flow for Cell-Aware Model GenerationP. d'Hondt, A. Ladhar, P. Girard, Arnaud Virazel. 484-488 [doi]
• DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMsZe-Wei Pan, Jin-Fu Li. 489-493 [doi]
• GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level DesignsMukta Debnath, Animesh Basak Chowdhury, Debasri Saha, Susmita Sur-Kolay. 494-498 [doi]
• Efficient Low Cost Alternative Testing of Analog Crossbar Arrays for Deep Neural NetworksKwondo Ma, Anurup Saha, Chandramouli N. Amarnath, Abhijit Chatterjee. 499-503 [doi]
• RIBoNN: Designing Robust In-Memory Binary Neural Network AcceleratorsShamik Kundu, Akul Malhotra, Arnab Raha, Sumeet Kumar Gupta, Kanad Basu. 504-508 [doi]
• Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite TestingPraise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi 0001, Degang Chen 0001. 509-513 [doi]
• Low Cost High Accuracy Stimulus Generator for On-chip Spectral TestingKushagra Bhatheja, Shravan K. Chaganti, Degang Chen 0001, Xiankun Robert Jin, Chris C. Dao, Juxiang Ren, Abhishek Kumar, Daniel Correa, Mark Lehmann, Thomas Rodriguez, Eric Kingham, Joel R. Knight, Allan Dobbin, Scott W. Herrin, Doug Garrity. 514-518 [doi]
• The Impact of On-chip Training to Adversarial Attacks in Memristive Crossbar ArraysBijay Raj Paudel, Spyros Tragoudas. 519-523 [doi]
• Runtime Fault Diagnostics for GPU Tensor CoresSaurabh Hukerikar, Nirmal R. Saxena. 524-528 [doi]
• Fault-coverage Maximizing March Tests for Memory TestingFeng Yun, Yunkun Lin, Lou Yunfei, Lei Gao, Vaibhav Gera, Boxuan Li, Vennela Chowdary Nekkanti, Aditya Rajendra Pharande, Kunal Sheth, Meghana Thommondru, Guizhong Ye, Sandeep Gupta. 529-533 [doi]
• Analyzing the Electromigration Challenges of Computation in Resistive MemoriesMahta Mayahinia, Mehdi B. Tahoori, Manu Perumkunnil, Kristof Croes, Francky Catthoor. 534-538 [doi]
• Circuit-to-Circuit Attacks in SoCs via Trojan-Infected IEEE 1687 Test InfrastructureMichele Portolan, Antonios Pavlidis, Giorgio Di Natale, Eric Faehn, Haralampos-G. Stratigopoulos. 539-543 [doi]
• Enhanced Data Pattern to Detect Defects in Flash Memory Address DecoderWeng Joe Soh, Chen He. 544-548 [doi]
• Wafer Defect Pattern Classification with Explainable-Decision Tree TechniqueKen Chau-Cheung Cheng, Katherine Shu-Min Li, Sying-Jyan Wang, Andrew Yi-Ann Huang, Chen-Shiun Lee, Leon Li-Yang Chen, Peter Yi-Yu Liao, Nova Cheng-Yen Tsai. 549-553 [doi]
• Yield-Enhanced Probe Head Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer TestNadun Sinhabahu, Katherine Shu-Min Li, Jian-De Li, J. R. Wang, Sying-Jyan Wang. 554-558 [doi]
• Virtual Prototyping: Closing the digital gap between product requirements and post-Si verificationThomas Nirmaier, Manuel Harrant, Marc Huppmann, Wendy You, Georg Pelz. 559-562 [doi]
• 4.5 Gsps MIPI D-PHY Receiver Circuit for Automatic Test EquipmentSeongkwan Lee, Cheolmin Park, Minho Kang, Jun Yeon Won, HyungSun Ryu, Jaemoo Choi, Byunghyun Yim. 563-567 [doi]
• Improvements in Automated IC Socket Pin Defect DetectionVijayakumar Thangamariappan, Nidhi Agrawal, Jason Kim, Constantinos Xanthopoulos, Ken Butler, Ira Leventhal, Joe Xiao. 568-572 [doi]
• Accurate Failure Rate Prediction Based on Gaussian Process Using WAT DataMakoto Eiki, Tomoki Nakamura, Masuo Kajiyama, Michiko Inoue, Michihiro Shintani. 573-577 [doi]
• Optimization of Tests for Managing Silicon Defects in Data CentersDavid P. Lerner, Benson Inkley, Shubhada H. Sahasrabudhe, Ethan Hansen, Luis D. Rojas Munoz, Arjan van de Ven. 578-582 [doi]
• Zero Trust Approach to IC Manufacturing and TestingBrian Buras, Constantinos Xanthopoulos, Ken Butler, Jason Kim. 583-586 [doi]
• Improving structural coverage of functional tests with checkpoint signature computationBenjamin Niewenhuis, Devanathan Varadarajan. 587-590 [doi]
• Fault Resilience Techniques for Flash Memory of DNN AcceleratorsShyue-Kung Lu, Yu-Sheng Wu, Jin-Hua Hong, Kohei Miyase. 591-600 [doi]
• Improving Test Quality of Memory Chips by a Decision Tree-Based Screening MethodYa-Chi Cheng, Pai-Yu Tan, Cheng-Wen Wu, Ming-Der Shieh, Chien-Hui Chuang, Gordon Liao. 601-608 [doi]
• Next Generation Design For Testability, Debug and Reliability Using Formal TechniquesSebastian Huhn 0001, Rolf Drechsler. 609-618 [doi]
• Testing of Analog Circuits using Statistical and Machine Learning TechniquesSupriyo Srimani, Hafizur Rahaman 0001. 619-626 [doi]
• AI-Driven Assurance of Hardware IP against Reverse Engineering AttacksPrabuddha Chakraborty, Swarup Bhunia. 627-636 [doi]
• High-Coverage DfT and Reliability Enhancements for Automotive Floating Gate OTP Beyond AEC-Q100Hans Martin von Staudt, Franz Schuler, Rohitaswa Bhattacharya, Justin Wei-Lin Cheng, Cheng-Da Huang, Parker Chih-Chun Chen. 637-641 [doi]
• A Novel Protection Technique for Embedded Memories with Optimized PPACostas Argyrides, Vilas Sridharan, Hayk Danoyan, Gurgen Harutyunyan, Yervant Zorian. 642-645 [doi]
• In-field Data Collection System through Logic BIST for large Automotive Systems-on-ChipGabriele Filipponi, Giusy Iaria, Matteo Sonza Reorda, Davide Appello, Giuseppe Garozzo, Vincenzo Tancorre. 646-649 [doi]
• An Efficient Test Strategy for Detection of Electromigration Impact in Advanced FinFET MemoriesMahta Mayahinia, Mehdi B. Tahoori, Gurgen Harutyunyan, Grigor Tshagharyan, Karen Amirkhanyan. 650-655 [doi]
• High Speed IO Access for Test forms the foundation for Silicon Lifecycle ManagementAmit Pandey, Brendan Tully, Karthikeyan Natarajan. 656-660 [doi]
• In search of Vmin for dynamic power managmenet and reliable operation in mission modeFirooz Massoudi. 661-664 [doi]