Table of Contents

• On the Evaluation of the PIPB Effect within SRAM-based FPGAsCorrado De Sio, Sarah Azimi, Luca Sterpone. 1-2 [doi]
• A Machine Learning-based Approach to Optimize Repair and Increase Yield of Embedded Flash Memories in Automotive Systems-on-ChipA. Manzini, P. Inglese, L. Caldi, R. Cantero, G. Carnevale, M. Coppetta, M. Giltrelli, N. Mautone, F. Irrera, Rudolf Ullmann, Paolo Bernardi. 1-6 [doi]
• Approximate computing design exploration through data lifetime metricsAlessandro Savino, Michele Portolan, Régis Leveugle, Stefano Di Carlo. 1-7 [doi]
• Model-driven AMS Test Setup Validation Tool prepared for IEEE P1687.2Leon M. A. van de Logt, Vladimir A. Zivkovic, Ingrid H. A. van Baast. 1-6 [doi]
• LearnX: A Hybrid Deterministic-Statistical Defect Diagnosis MethodologySoumya Mittal, R. D. Shawn Blanton. 1-6 [doi]
• On Integrating Lightweight Encryption in Reconfigurable Scan NetworksBenjamin Thiemann, Linus Feiten, Pascal Raiola, Bernd Becker 0001, Matthias Sauer 0002. 1-6 [doi]
• Non-Adaptive Pattern Reordering to Improve Scan Chain Diagnostic ResolutionYu Huang 0005, Jakub Janicki, Szczepan Urban. 1-6 [doi]
• Exploring Algebraic Interpolants for Rectification of Finite Field Arithmetic Circuits with Gröbner BasesUtkarsh Gupta, Priyank Kalla, Irina Ilioaea, Florian Enescu. 1-6 [doi]
• Impact of Reduced Precision in the Reliability of Deep Neural Networks for Object DetectionFernando Fernandes dos Santos, Philippe O. A. Navaux, Luigi Carro, Paolo Rech. 1-6 [doi]
• DFT Scheme for Hard-to-Detect Faults in FinFET SRAMsGuilherme Cardoso Medeiros, Mottaqiallah Taouil, Moritz Fieback, Leticia Bolzani Poehls, Said Hamdioui. 1-2 [doi]
• A 52 dB-SFDR 166 MHz sinusoidal signal generator for mixed-signal BIST applications in 28 nm FDSOI technologyHani Malloug, Manuel J. Barragan, Salvador Mir. 1-6 [doi]
• A Dynamic Greedy Test Scheduler for Optimizing Probe Motion in In-Circuit TestersLuciano Bonaria, M. Raganato, Matteo Sonza Reorda, Giovanni Squillero. 1-2 [doi]
• Dependable Wireless Industrial IoT Networks: Recent Advances and Open ChallengesFotis Foukalas, Paul Pop, Fabrice Theoleyre, Carlo Alberto Boano, Chiara Buratti. 1-10 [doi]
• Digital Built-in Self-Test for Phased Locked Loops to Enable Fault DetectionMehmet Ince, Ender Yilmaz, Wei Fu, Joonsung Park, Krishnaswamy Nagaraj, LeRoy Winemberg, Sule Ozev. 1-6 [doi]
• Inter-Lock: Logic Encryption for Processor Cores Beyond Module BoundariesDominik Sisejkovic, Farhad Merchant, Rainer Leupers, Gerd Ascheid, Sascha Kegreiss. 1-6 [doi]
• IJTAG Compatible Timing Monitor with Robust Self-Calibration for Environmental and Aging VariationGhazanfar Ali, Jerrin Pathrose, Hans G. Kerkhoff. 1-6 [doi]
• A supervised machine learning application in volume diagnosisYue Tian, Gaurav Veda, Wu-Tung Cheng, Manish Sharma, Huaxing Tang, Neerja Bawaskar, Sudhakar M. Reddy. 1-6 [doi]
• Revisiting Logic Locking for Reversible ComputingNimisha Limaye, Muhammad Yasin, Ozgur Sinanoglu. 1-6 [doi]
• Post-Silicon Validation of IEEE 1687 Reconfigurable Scan NetworksAleksa Damljanovic, Artur Jutman, Giovanni Squillero, Anton Tsertov. 1-6 [doi]
• STAHL: A Novel Scan-Test-Aware Hardened Latch DesignRuijun Ma, Stefan Holst, Xiaoqing Wen, Aibin Yan, Hui Xu. 1-6 [doi]
• Test Solutions for High Density 3D-IC Interconnects - Focus on SRAM-on-Logic PartitioningImed Jani, Didier Lattard, Pascal Vivet, Jean Durupt, Sebastien Thuries, Edith Beigné. 1-2 [doi]
• Symbolic Circuit Analysis under an Arc Based Timing ModelGörschwin Fey, Alberto García Ortiz. 1-2 [doi]
• Machine Learning-based Prediction of Test PowerHarshad Dhotre, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler. 1-6 [doi]
• Security in Autonomous SystemsStefan Katzenbeisser, Ilia Polian, Francesco Regazzoni, Marc Stöttinger. 1-8 [doi]
• Test Adapted Shielding by a Multipurpose Crosstalk Avoidance SchemeMahsa Akhsham, Atefesadat Seyedolhosseini, Zainalabedin Navabi. 1-2 [doi]
• Hardware-Based Aging Mitigation Scheme for Memory Address DecoderDaniel Kraak, Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor. 1-6 [doi]
• Power Measurement and Spectral Test of ZigBee Transmitters from 1-bit Under-sampled AcquisitionT. Vayssade, Florence Azaïs, Laurent Latorre, Francois Lefevre. 1-6 [doi]
• On Generating Fault Diagnosis Patterns for Designs with X SourcesXijiang Lin, Sudhakar M. Reddy. 1-6 [doi]
• A Functional Approach to Test and Debug of IEEE 1687 Reconfigurable NetworksMichele Portolan, Riccardo Cantoro, Ernesto Sánchez 0001. 1-2 [doi]
• PaTran: Translation Platform for Test Pattern ProgramJung-Geun Park, Minsu Kim, Soo-Mook Moon, Sungyeol Kim, Insu Yang, Hyunsoo Jung. 1-2 [doi]
• Concurrent Estimation of a PLL Transfer Function by Cross-Correlation with pseudo-random JitterJan Schat, Ulrich Möhlmann. 1-2 [doi]
• K3 TAM Optimization for Testing 3D-SoCs using Non-Regular Time-Division-MultiplexingPanagiotis Georgiou, Iakovos Theodosopoulos, Xrysovalantis Kavousianos. 1-6 [doi]
• High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC ProcessorsAdeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik. 1-6 [doi]
• B-open: A New Defect in Nanometer Technologies due to SADP ProcessFreddy Forero, Michel Renovell, Víctor H. Champac. 1-2 [doi]
• Pinhole Defect Characterization and Fault Modeling for STT-MRAM TestingLizhou Wu, Siddharth Rao, Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Erik Jan Marinissen, Farrukh Yasin, Sebastien Couet, Said Hamdioui, Gouri Sankar Kar. 1-6 [doi]
• Feature Engineering for Recycled FPGA Detection Based on WID Variation ModelingFoisal Ahmed, Michihiro Shintani, Michiko Inoue. 1-2 [doi]
• Back-annotation of Interconnect Physical Properties for System-Level Crosstalk ModelingRezgar Sadeghi, Nooshin Nosrati, Katayoon Basharkhah, Zainalabedin Navabi. 1-6 [doi]
• Test Pattern Generator for Majority Voter based QCA Combinational Circuits targeting MMC DefectVaishali Dhare, Usha Mehta. 1-2 [doi]
• Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICsArjun Chaudhuri, Sanmitra Banerjee, Heechun Park, Bon Woong Ku, Krishnendu Chakrabarty, Sung Kyu Lim. 1-6 [doi]
• Alternatives to Fault Injections for Early Safety/Security EvaluationsMichele Portolan, Alessandro Savino, Régis Leveugle, Stefano Di Carlo, Alberto Bosio, Giorgio Di Natale. 1-10 [doi]
• Hybrid Architecture for Embedded Test Compression to Process Rejected Test PatternsSebastian Huhn 0001, Daniel Tille, Rolf Drechsler. 1-2 [doi]