Table of Contents

• A Hybrid Space Compactor for Adaptive X-HandlingMohammad Urf Maaz, Alexander Sprenger, Sybille Hellebrand. 1-8 [doi]
• Testing Computation-in-Memory Architectures Based on Emerging MemoriesSaid Hamdioui, Moritz Fieback, Surya Nagarajan, Mottaqiallah Taouil. 1-10 [doi]
• Device-Aware Test: A New Test Approach Towards DPPB LevelMoritz Fieback, Lizhou Wu, Guilherme Cardoso Medeiros, Hassen Aziza, Siddharth Rao, Erik Jan Marinissen, Mottaqiallah Taouil, Said Hamdioui. 1-10 [doi]
• Is Backside the New Backdoor in Modern SoCs?: Invited PaperNidish Vashistha, M. Tanjidur Rahman, Olivia P. Paradis, Navid Asadizanjani. 1-10 [doi]
• Variation-Aware Small Delay Fault Diagnosis on Compressed Test ResponsesStefan Holst, Eric Schneider, Michael A. Kochte, Xiaoqing Wen, Hans-Joachim Wunderlich. 1-10 [doi]
• A Framework for Design of Self-Repairing Digital SystemsJingchi Yang, David C. Keezer. 1-10 [doi]
• Improving Test Chip Design Efficiency via Machine LearningZeye Liu 0001, Qicheng Huang, Chenlei Fang, R. D. (Shawn) Blanton. 1-10 [doi]
• A New Test Method for the Large Current Magnetic SensorsToshiyuki Omuro, Shigeo Nakamura Surname, Takashi Kimura, Kiyokawa Omuro. 1-7 [doi]
• An Overview of the International Microprocessor/ SoC Test, Security and Validation (MTV)WorkshopMagdy Abadir, Sohrab Aftabjahani. 1-2 [doi]
• Security Compliance Analysis of Reconfigurable Scan NetworksNatalia Lylina, Ahmed Atteya, Pascal Raiola, Matthias Sauer 0002, Bernd Becker 0001, Hans-Joachim Wunderlich. 1-9 [doi]
• Multi-cell characterization: Developing robust cells and abstraction for Rapid Single Flux Quantum (RSFQ) LogicFangzhou Wang, Sandeep K. Gupta. 1-10 [doi]
• Test Time and Area Optimized BrST Scheme for Automotive ICsNilanjan Mukherjee 0001, Jerzy Tyszer, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki. 1-10 [doi]
• Efficient Analog Defect SimulationStephen Sunter. 1-10 [doi]
• IEEE International Symposium on Hardware Oriented Security and Trust (HOST): Past, Present, and FutureDomenic Forte, Swarup Bhunia, Ramesh Karri, Jim Plusquellic, Mark Tehranipoor. 1-4 [doi]
• Characterization of Locked Combinational Circuits via ATPGDanielle Duvalsaint, Xiaoxiao Jin, Benjamin Niewenhuis, R. D. (Shawn) Blanton. 1-10 [doi]
• Knowledge Transfer in Board-Level Functional Fault Identification using Domain AdaptationMengyun Liu, Xin Li, Krishnendu Chakrabarty, Xinli Gu. 1-10 [doi]
• VIPER: A Versatile and Intuitive Pattern GenERator for Early Design Space ExplorationGaurav Rajavendra Reddy, Mohammad-Mahdi Bidmeshki, Yiorgos Makris. 1-7 [doi]
• Iterative Test Generation for Gate-Exhaustive Faults to Cover the Sites of Undetectable Target FaultsIrith Pomeranz. 1-7 [doi]
• TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield LearningAndrew Yi-Ann Huang, Katherine Shu-Min Li, Cheng-Yen Tsai, Ken Chau-Cheung Cheng, Sying-Jyan Wang, Xu-Hao Jiang, Leon Chou, Chen-Shiun Lee. 1-6 [doi]
• Memory FIT Rate Mitigation Technique for Automotive SoCsGabriele Boschi, Donato Luongo, Duccio Lazzarotti, Hanna Shaheen, Hayk Grigoryan, Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian. 1-6 [doi]
• Time-Slicing Soft Error Resilience in Microprocessors for Reliable and Energy-Efficient ExecutionYi He, Yanjing Li. 1-10 [doi]
• Advanced Burn-In - An Optimized Product Stress and Test Flow for Automotive MicrocontrollersChen He. 1-6 [doi]
• Testing of Neuromorphic Circuits: Structural vs FunctionalAnteneh Gebregiorgis, Mehdi Baradaran Tahoori. 1-10 [doi]
• Simulation-based Equivalence Checking between IEEE 1687 ICL and RTLAleksa Damljanovic, Artur Jutman, Michele Portolan, Ernesto Sánchez 0001, Giovanni Squillero, Anton Tsertov. 1-8 [doi]
• DARS: An EDA Framework for Reliability and Functional Safety Management of System-on-ChipsAhmed M. Y. Ibrahim, Hans G. Kerkhoff. 1-10 [doi]
• A Jitter Injection Module for Production Test of 52-Gbps PAM4 Signal InterfacesKiyotaka Ichiyama, Takashi Kusaka, Masahiro Ishida. 1-8 [doi]
• FPGA Bitstream Security: A Day in the LifeAdam Duncan, Fahim Rahman, Andrew Lukefahr, Farimah Farahmandi, Mark Tehranipoor. 1-10 [doi]
• Overall Strategy for Online Clock System Checking Supporting Heterogeneous IntegrationWei Chu, Shi-Yu Huang. 1-10 [doi]
• Machine Learning-Based DFT Recommendation System for ATPG QORApik Zorian, Basim Shanyour, Milir Vaseekar. 1-7 [doi]
• Deploying A Machine Learning Solution As A SurrogateChuanhe Jay Shan, Ahmed Wahba, Li-C. Wang, Nik Sumikawa. 1-10 [doi]
• Subtle Anomaly Detection of Microscopic Probes using Deep learning based Image CompletionKosuke Ikeda, Keith Schaub, Ira Leventhal, Yiorgos Makris, Constantinos Xanthopoulos, Deepika Neethirajan. 1-3 [doi]
• An Overview of the International Verification and Security Workshop (IVSW)Magdy Abadir, Sohrab Aftabjahani. 1-2 [doi]
• Towards Complete Fault Coverage by Test Point Insertion using Optimization-SAT TechniquesStephan Eggersglüß. 1-8 [doi]
• Fault Recovery in Micro-Electrode-Dot-Array Digital Microfluidic Biochips Using an IJTAG NetworkBehaviorsZhanwei Zhong, Krishnendu Chakrabarty. 1-10 [doi]
• Applying Vstress and defect activation coverage to produce zero-defect mixed-signal automotive ICsWim Dobbelaere, Frederik Colle, Anthony Coyette, Ronny Vanhooren, Nektar Xama, Jhon Gomez, Georges G. E. Gielen. 1-4 [doi]
• 17th IEEE East-West Design and Test SymposiumYervant Zorian, Vladimir Hahanov, Svetlana Chumachenko, Eugenia Litvinova. 1-4 [doi]
• Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive ApplicationsChristos Papameletis, Vivek Chickermane, Brian Foutz, Sarthak Singhal, Krishna Chakravadhanula. 1-6 [doi]
• Programmable Daisychaining of Microelectrodes for IP Protection in MEDA BiochipsTung-Che Liang, Krishnendu Chakrabarty, Ramesh Karri. 1-10 [doi]
• FAE: Autoencoder-Based Failure Binning of RTL Designs for Verification and DebuggingCheng-Hsien Shen, Aaron C.-W. Liang, Charles C.-H. Hsu, Charles H.-P. Wen. 1-10 [doi]
• Armenia: Communicating to World Community in Electronic Test and DesignSamvel K. Shoukourian, Yuri Shoukourian, Vladimir Sahakyan. 1-3 [doi]
• Application of Cell-Aware Test on an Advanced 3nm CMOS Technology LibraryZhan Gao, Santosh Malagi, Min-Chun Hu, Joe Swenton, Rogier Baert, Jos Huisken, Bilal Chehab, Kees Goossens, Erik Jan Marinissen. 1-6 [doi]
• An Adaptive Approach to Minimize System Level Tests Targeting Low Voltage DVFS FailuresAdit D. Singh. 1-10 [doi]
• Applications of Hierarchical TestKelly Ockunzzi, Richard Grupp, Brion Keller, Mark Taylor, Sreekanth Pai, Greeshma Jayakumar. 1-6 [doi]
• th Generation Intel® Core™ MicroprocessorsGerhard Schrom, Michael J. Hill, Sarath Makala, Ravi Sankar Vunnam, Arun Krishnamoorthy, Ryan Ferguson. 1-6 [doi]
• China Test Conference (CTC) - Extending the Global Test Forum to ChinaHuawei Li, Xiaowei Li 0001, Yinhe Han. 1-4 [doi]
• A Decentralized Scheduler for On-line Self-test Routines in Multi-core Automotive System-on-ChipsAndrea Floridia, Davide Piumatti, Annachiara Ruospo, Ernesto Sánchez 0001, Sergio de Luca, Rosario Martorana. 1-10 [doi]
• Recycled Analog and Mixed Signal Chip Detection at Zero Cost Using LDO DegradationSreeja Chowdhury, Fatemeh Ganji, Troy Bryant, Nima Maghari, Domenic Forte. 1-10 [doi]
• Virtual Memory Structures Facilitating Memory BIST Insertion In Complex SoCsTal Kogan, Yehonatan Abotbol. 1-3 [doi]
• Characterization of Library Cells for Open-circuit Defect Exposure: A Systematic MethodologySujay Pandey, Sanya Gupta, Madhu Sudhan L., Suriya Natarajan, Arani Sinha, Abhijit Chatterjee. 1-10 [doi]
• Asian Test Symposium - Past, Present and Future -Michiko Inoue, Xiaowei Li 0001, Cheng-Wen Wu. 1-4 [doi]
• Resiliency of automotive object detection networks on GPU architecturesAtieh Lotfi, Saurabh Hukerikar, Keshav Balasubramanian, Paul Racunas, Nirmal R. Saxena, Richard Bramley, Yanxiang Huang. 1-9 [doi]
• SoC Security Verification using Property CheckingNusrat Farzana, Fahim Rahman, Mark Tehranipoor, Farimah Farahmandi. 1-10 [doi]
• IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR)Szilárd Enyedi, Liviu Miclea. 1-4 [doi]
• Fault-Tolerant Neuromorphic Computing SystemsArjun Chaudhuri, Mengyun Liu, Krishnendu Chakrabarty. 1-10 [doi]
• High Quality Test Methodology for Highly Reliable DevicesHao Chen, Mincent Lee, Liang-Yen Chen, Min-Jer Wang. 1-6 [doi]
• On Freedom from Interference in Mixed-Criticality Systems: A Causal Learning ApproachFei Su, Prashant Goteti, Min Zhang. 1-10 [doi]
• International Symposium on Design and Diagnostics of Electronic Circuits and SystemsZoran Stamenkovic, Alberto Bosio, György Cserey, Ondrej Novák, Witold A. Pleskacz, Lukás Sekanina, Andreas Steininger, Goran Stojanovic, Viera Stopjaková. 1-4 [doi]
• Methodology of Generating Timing-Slack-Based Cell-Aware TestsYu-Teng Nien, Kai-Chiang Wu, Dong-Zhen Lee, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao. 1-10 [doi]
• An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed TestSeyed Nima Mozaffari, Bonita Bhaskaran, Kaushik Narayanun, Ayub Abdollahian, Vinod Pagalone, Shantanu Sarangi, Jonathon E. Colburn. 1-10 [doi]
• Built-in self-test and self-calibration for analog and mixed signal circuitsTao Chen 0006, Degang Chen. 1-8 [doi]
• Machine Learning-Based Automatic Generation of eFuse Configuration in NAND Flash ChipJisuk Kim, Jinyub Lee, Sungjoo Yoo. 1-9 [doi]
• Hardware Fault Tolerance for Binary RRAM CrossbarsArjun Chaudhuri, Bonan Yan, Yiran Chen, Krishnendu Chakrabarty. 1-10 [doi]
• International Test Conference in Asia (ITC-Asia) - Bridging ITC and Test Community in AsiaKuen-Jong Lee, Shi-Yu Huang, Huawei Li, Tomoo Inoue, Yervant Zorian. 1-4 [doi]
• IEEE European Test Symposium (ETS)Stephan Eggersglüß, Said Hamdioui, Artur Jutman, Maria K. Michael, Jaan Raik, Matteo Sonza Reorda, Mehdi Baradaran Tahoori, Elena Ioana Vatajelu. 1-4 [doi]
• Breaking Analog Locking Techniques via Satisfiability Modulo TheoriesNithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Amr Abuellil, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran. 1-10 [doi]
• The Challenges of Implementing an MBIST Interface: A Practical ApplicationTeresa McLaurin, Rob Knoth. 1-6 [doi]
• Effectively Using Machine Learning to Expedite System Level Test Failure DebugLuis D. Rojas, Kevin Hess, Christina Carter-Brown. 1-6 [doi]
• Safety Design of a Convolutional Neural Network Accelerator with Error Localization and CorrectionZheng Xu, Jacob Abraham. 1-10 [doi]
• Compaction of a Functional Broadside Test Set through the Compaction of a Functional Test Sequence without Sequential Fault SimulationIrith Pomeranz. 1-7 [doi]
• Structural Test and Functional Test for Digital Acoustofluidic BiochipsZhanwei Zhong, Haodong Zhu, Peiran Zhang, Tony Jun Huang, Krishnendu Chakrabarty. 1-10 [doi]
• Reliability Modeling and Mitigation for Embedded MemoriesInnocent Okwudili Agbo, Mottaqiallah Taouil, Said Hamdioui. 1-10 [doi]
• IEEE Std. P1687.1: Translator and ProtocolErik Larsson, Prathamesh Murali, Gani Kumisbek. 1-10 [doi]