Table of Contents

• "Safe" built-in test and tuning of boost converters using feedback loop perturbationsXian Wang, Kenfack Blanchard, Estella Silva, Abhijit Chatterjee. 1-6 [doi]
• CMOS amplifier with self-correction offset for SerDes applicationsRigoberto Bracamontes-Salazar, Esdras Juarez Hernandez, Federico Lobato-Lopez, Esteban Martinez Guerrero. 1-4 [doi]
• Ringing error prevention techniques in Lucy-Richardson deconvolution process for SRAM space-time margin variation effect screening designsHiroyuki Yamauchi, Worawit Somha. 1-6 [doi]
• A virtual instrument design for low-cost charge-pumping characterization of integrated MOSFETsJailene Hernandez, Johan Castrillon, Manuel Jimenez, Angel de la Torre, Pedro Escalona, Rogelio Palomera. 1-4 [doi]
• Improvement of a detection chain based on a VCO concept for microelectronic reliability under natural radiative environmentKarine Coulié-Castellani, Wenceslas Rahajandraibe, Hassen Aziza, Jean Michel Portal, Gilles Micolau. 1-5 [doi]
• A multi-layer software-based fault-tolerance approach for heterogenous multi-core systemsS. Müller, Tobias Koal, S. Scharoba, Heinrich Theodor Vierhaus, Mario Schölzel. 1-6 [doi]
• Adopting multi-valued logic for reduced pin-count testingBaohu Li, Bei Zhang, Vishwani D. Agrawal. 1-6 [doi]
• Exemplar-based failure triage for regression design debuggingZissis Poulos, Andreas G. Veneris. 1-6 [doi]
• Generation and performance evaluation of reconfigurable random routing algorithm for 2D-mesh NoCsSandeep Kumar Singh, Abir J. Mondal, Alak Majumder. 1-6 [doi]
• Design dependent SRAM PUF robustness analysisMafalda Cortez, Said Hamdioui, Ryoichi Ishihara. 1-6 [doi]
• Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cellHector Villacorta, Roberto Gómez, Sebastiàn Bota, Jaume Segura, Víctor H. Champac. 1-6 [doi]
• Complex delay fault reasoning with sequential 7-valued algebraJaak Kousaar, Raimund Ubar, Igor Aleksejev. 1-6 [doi]
• A digital technique for the evaluation of SSB phase noise of analog/RF signalsFlorence Azaïs, Stephane David-Grignot, Laurent Latorre, Francois Lefevre. 1-6 [doi]
• Test set generation almost for free using a run-time FPGA reconfiguration techniqueAlexandra Kourfali, Dirk Stroobandt. 1-6 [doi]
• Design of ultra-low-power smart wearable systemsGregoire Surrel, Francisco J. Rincón, Srinivasan Murali, David Atienza. 1-2 [doi]
• Message from the LATS2015 ChairsVíctor H. Champac, Yervant Zorian, Letícia Maria Bolzani Pöhls, Vishwani D. Agrawal. 1 [doi]
• Impedance matching analysis and EMC validation of a low-cost PCB differential interconnectJ. Rafael del-Rey, Zabdiel Brito-Brito, José Ernesto Rayas-Sánchez. 1-5 [doi]
• Using only redundant modules with approximate logic to reduce drastically area overhead in TMRIuri A. C. Gomes, Mayler G. A. Martins, André Inácio Reis, Fernanda Lima Kastensmidt. 1-6 [doi]
• Vericonn: a tool to generate efficient interconnection networks for post-silicon debugAndré B. M. Gomes, Fredy A. M. Alves, Ricardo S. Ferreira, José Augusto Miranda Nacif. 1-6 [doi]
• Multiple fault injection platform for SRAM-based FPGA based on ground-level radiation experimentsJimmy Tarrillo, Jorge Tonfat, Lucas A. Tambara, Fernanda Lima Kastensmidt, Ricardo Reis. 1-6 [doi]
• In-field test of safety-critical systems: is functional test a feasible solution?Matteo Sonza Reorda. 1-2 [doi]
• Single event effects in an analog SOI transconductor: a case studyCarlos Viale, Pablo A. Petrashin, Luis E. Toledo, Walter J. Lancioni, Carlos Vázquez. 1-4 [doi]
• SW-based transparent in-field memory testingPaolo Bernardi, Lyl M. Ciganda Brasca, Matteo Sonza Reorda, Said Hamdioui. 1-6 [doi]
• Study of regression methodologies on analog circuit designIvick Guerra-Gómez, Trent McConaghy, Esteban Tlelo-Cuautle. 1-6 [doi]
• Transformations on the FSMD of the RTL code with combinational logic statements for equivalence checking of HLSRaul Acosta Hernandez, Marius Strum, Wang Jiang Chau. 1-6 [doi]
• Estimation of dynamic current waveforms using pre-characterization of standard cellsBharath Shivashankar, Michael Skaggs, Sushmita Kadiyala Rao, Ryan Robucci, Nilanjan Banerjee, Chintan Patel. 1-6 [doi]
• Scan based two-pattern tests: should they target opens instead of TDFs?Adit D. Singh. 1-2 [doi]
• Noise analysis of integrated bulk current sensors for detection of radiation induced soft errorsJoao Guilherme Mourao Melo, Frank Sill Torres. 1-6 [doi]
• Rare event diagnosis by iterative failure region locating and elite learning sample selectionHosoon Shin, Sheldon X.-D. Tan, Guoyong Shi, Esteban Tlelo-Cuautle. 1-5 [doi]
• Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPGN. Palermo, Valentin Tihhomirov, Thiago Santos Copetti, Maksim Jenihhin, Jaan Raik, Sergei Kostin, Marco Gaudesi, Giovanni Squillero, Matteo Sonza Reorda, F. Vargas, Letícia Maria Bolzani Pöhls. 1-6 [doi]
• NBTI-induced circuit aging optimization by protectability-aware gate replacement techniqueGuimao Zhang, Maoxiang Yi, Yong Miao, Dawen Xu, Huaguo Liang. 1-4 [doi]
• A method of one-pass seed generation for LFSR-based deterministic/pseudo-random testing of static faultsTakanori Moriyasu, Satoshi Ohtake. 1-6 [doi]
• Fault-tolerance in FPGA focusing power reduction or performance enhancementCarlos Leong, Jorge Semião, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. 1-6 [doi]
• Optimizing operational amplifiers by metaheuristics and considering tolerance analysisLuis Gerardo de la Fraga, Esteban Tlelo-Cuautle. 1-4 [doi]
• Fault conditions of a simple chaotic circuit under capacitor nonlinear effectsJ. L. Bueno-Ruiz, C. A. Arriaga-Arriaga, R. Huerta-Barrera, G. V. Cruz-Dominguez, C. H. Pimentel-Romero, Jesús M. Muñoz-Pacheco, L. C. Gómez-Pavón, O. G. Félix-Beltrán, A. Luis-Ramos. 1-5 [doi]
• Test compression for circuits with multiple scan chainsOndrej Novák, Jiri Jenícek, Martin Rozkovec. 1-6 [doi]
• An evolutionary approach for test program compactionR. Cantoro, Marco Gaudesi, Ernesto Sanchez, P. Schiavone, Giovanni Squillero. 1-6 [doi]
• Permanent fault detection and diagnosis in the lightweight dual modular redundancy architectureRonaldo Rodrigues Ferreira, Ernesto Sánchez, Jean da Rolt, Gabriel L. Nazar, Álvaro F. Moreira, Luigi Carro, Matteo Sonza Reorda. 1-6 [doi]
• A controllable setup and propagation delay flip-flop designAlexandro Giron-Allende, Victor Avendaño, Esteban Martinez Guerrero. 1-5 [doi]
• Considerations on application of selective hardening based on software fault tolerance techniquesFelipe Restrepo-Calle, Sergio Cuenca-Asensi, Antonio Martínez-Álvarez, Fernanda Lima Kastensmidt. 1-6 [doi]
• Low cost built-in-tuning of on-chip passive filters for low-if double quadrature rf receiverWenceslas Rahajandraibe, Fayrouz Haddad, Hassen Aziza, K. Castellani-Coulié, Jean Michel Portal. 1-4 [doi]
• Power distribution network analysis using semi irregular plane shape approach and via modelingAntonio Zenteno Ramírez. 1-6 [doi]
• NBTI-aware design of integrated circuits: a hardware-based approachThiago Copetti, G. Cardoso Medeiros, Letícia Maria Bolzani Poehls, Fabian Vargas. 1-6 [doi]
• Improving logic obfuscation via logic cone analysisYu-Wei Lee, Nur A. Touba. 1-6 [doi]
• Virtual reconfigurable scan-chains on FPGAs for optimized board testIgor Aleksejev, Sergei Devadze, Artur Jutman, Konstantin Shibin. 1-6 [doi]
• Optimizing an LDO voltage regulator by evolutionary algorithms considering tolerances of the circuit elementsJesus Lopez-Arredondo, Esteban Tlelo-Cuautle, Rodolfo Trejo-Guerra. 1-5 [doi]
• Efficient fault injection in QEMUDavide Ferraretto, Graziano Pravadelli. 1-6 [doi]
• Effective selection of favorable gates in BTI-critical paths to enhance circuit reliabilityAndres Gomez, Víctor H. Champac. 1-6 [doi]
• FPGA redundancy recovery based on partial bitstreams for multiple partitionsVictor M. Goncalves Martins, Joao Gabriel Reis, Horacio C. C. Netoy, Eduardo Augusto Bezerra. 1-4 [doi]