Abstract is missing.
- At-speed on-chip diagnosis of board-level interconnect faultsArtur Jutman. 2-7 [doi]
- Accurate tap-delay measurements using a di .erential oscillation techniqueOctavian Petre, H. G. Kerkho. 10-15 [doi]
- Delay chain based programmable jitter generatorTian Xia, Peilin Song, Keith A. Jenkins, Jien-Chung Lo. 16-21 [doi]
- Application of local design-for-reliability techniques for reducing wear-out degradation of CMOS combinational logic circuitsXiangdong Xuan, Abhijit Chatterjee, Adit D. Singh. 24-29 [doi]
- A new self-checking multiplier by use of a code-disjoint sum-bit duplicated adderDaniel Marienfeld, Egor S. Sogomonyan, Vitalij Ocheretnij, Michael Gössel. 30-35 [doi]
- Software development for an open architecture test systemBruce R. Parnas, Ankan K. Pramanick, Mark Elston, Toshiaki Adachi. 38-43 [doi]
- Delay fault testing and silicon debug using scan chainsRamyanshu Datta, Antony Sebastine, Jacob A. Abraham. 46-51 [doi]
- Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAsPatrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell. 52-57 [doi]
- Electrically-induced thermal stimuli for MEMS testingNorbert Dumas, Florence Azaïs, Laurent Latorre, Pascal Nouet. 60-65 [doi]
- Mems built-in-self-test using MLSAchraf Dhayni, Salvador Mir, Libor Rufer. 66-71 [doi]
- Test planning and test resource optimization for droplet-based microfluidic systemsFei Su, Sule Ozev, Krishnendu Chakrabarty. 72-77 [doi]
- User-constrained test architecture design for modular SOC testingLudovic A. Krundel, Sandeep Kumar Goel, Erik Jan Marinissen, Marie-Lise Flottes, Bruno Rouzeyre. 80-85 [doi]
- Pipelined test of SOC cores through test data transformationsOzgur Sinanoglu, Alex Orailoglu. 86-91 [doi]
- Relating entropy theory to test data compressionKedarnath J. Balakrishnan, Nur A. Touba. 94-99 [doi]
- A compression-driven test access mechanism design approachPaul Theo Gonciari, Bashir M. Al-Hashimi. 100-105 [doi]
- Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic valuesSeiji Kajihara, Kewal K. Saluja, Sudhakar M. Reddy. 108-113 [doi]
- Signal integrity verification using high speed monitorsVictor Avendaño, Víctor H. Champac, Joan Figueras. 114-119 [doi]
- Towards a BIST technique for noise figure evaluationMarcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin. 122-126 [doi]
- A new BIST scheme for 5GHz low noise amplifiersJee-Youl Ryu, Bruce C. Kim, Iboun Taimiya Sylla. 127-132 [doi]
- All-pass SC biquad reconfiguration scheme for oscillation based analog BISTUros Kac, Franc Novak. 133-138 [doi]
- Dynamic read destructive fault in embedded-SRAMs: analysis and march test solutionLuigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan. 140-145 [doi]
- Tests for address decoder delay faults in RAMs due to inter-gate opensA. J. van de Goor, Said Hamdioui, Zaid Al-Ars. 146-151 [doi]
- Functional fault coverage: the chamber of secrets or an accurate estimation of gate-level coverage?Franco Fummi, Cristina Marconcini, Graziano Pravadelli. 154-159 [doi]
- Automatic test pattern generation for resistive bridging faultsPiet Engelke, Ilia Polian, Michel Renovell, Bernd Becker. 160-165 [doi]
- A design methodology to realize delay testable controllers using state transition informationTsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara. 168-173 [doi]
- An efficient scan tree design for test time reductionYannick Bonhomme, Tomokazu Yoneda, Hideo Fujiwara, Patrick Girard. 174-179 [doi]