Application of local design-for-reliability techniques for reducing wear-out degradation of CMOS combinational logic circuits - researchr publication

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Xiangdong Xuan, Abhijit Chatterjee, Adit D. Singh. Application of local design-for-reliability techniques for reducing wear-out degradation of CMOS combinational logic circuits. In 9th European Test Symposium (ETS 2004), May 23-26, 2004, Ajaccio, France. pages 24-29, IEEE, 2004. [doi]

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