Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values - researchr publication

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Seiji Kajihara, Kewal K. Saluja, Sudhakar M. Reddy. Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values. In 9th European Test Symposium (ETS 2004), May 23-26, 2004, Ajaccio, France. pages 108-113, IEEE, 2004. [doi]

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