Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Seiji Kajihara, Kewal K. Saluja, Sudhakar M. Reddy. Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values. In 9th European Test Symposium (ETS 2004), May 23-26, 2004, Ajaccio, France. pages 108-113, IEEE, 2004. [doi]

This author has not been identified. Look up 'Seiji Kajihara' in GoogleThis author has not been identified. Look up 'Kewal K. Saluja' in GoogleThis author has not been identified. Look up 'Sudhakar M. Reddy' in Google

runs on WebDSL