Seiji Kajihara, Kewal K. Saluja, Sudhakar M. Reddy. Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values. In 9th European Test Symposium (ETS 2004), May 23-26, 2004, Ajaccio, France. pages 108-113, IEEE, 2004. [doi]
@inproceedings{KajiharaSR04,
title = {Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values},
author = {Seiji Kajihara and Kewal K. Saluja and Sudhakar M. Reddy},
year = {2004},
doi = {10.1109/ETSYM.2004.1347620},
url = {http://doi.ieeecomputersociety.org/10.1109/ETSYM.2004.1347620},
researchr = {https://researchr.org/publication/KajiharaSR04},
cites = {0},
citedby = {0},
pages = {108-113},
booktitle = {9th European Test Symposium (ETS 2004), May 23-26, 2004, Ajaccio, France},
publisher = {IEEE},
isbn = {0-7695-2119-3},
}