Abstract is missing.
- A brand new wireless dayJan M. Rabaey. 1 [doi]
- Variability-driven module selection with joint design time optimization and post-silicon tuningFeng Wang 0004, Xiaoxia Wu, Yuan Xie. 2-9 [doi]
- Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGACheng-Tao Hsieh, Jason Cong, Zhiru Zhang, Shih-Chieh Chang. 10-15 [doi]
- A multicycle communication architecture and synthesis flow for Global interconnect Resource SharingWei-Sheng Huang, Yu-Ru Hong, Juinn-Dar Huang, Ya-Shih Huang. 16-21 [doi]
- Scheduling with integer time budgeting for low-power optimizationWei Jiang, Zhiru Zhang, Miodrag Potkonjak, Jason Cong. 22-27 [doi]
- REWIRED - Register Write Inhibition by Resource DedicationPushkar Tripathi, Rohan Jain, Srikanth Kurra, Preeti Ranjan Panda. 28-31 [doi]
- An efficient performance improvement method utilizing specialized functional units in Behavioral SynthesisTsuyoshi Sadakata, Yusuke Matsunaga. 32-35 [doi]
- Predictive power aware management for embedded mobile devicesYoung-Si Hwang, Sung-Kwan Ku, Chan-Min Jung, Ki-Seok Chung. 36-41 [doi]
- A dynamic-programming algorithm for reducing the energy consumption of pipelined System-Level streaming applicationsNikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee. 42-48 [doi]
- Temperature-aware MPSoC scheduling for reducing hot spots and gradientsAyse Kivilcim Coskun, Tajana Simunic Rosing, Keith Whisnant, Kenny C. Gross. 49-54 [doi]
- Run-time power gating of on-chip routers using look-ahead routingHiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang. 55-60 [doi]
- Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architecturesSushu Zhang, Karam S. Chatha. 61-66 [doi]
- Statistical power profile correlation for realistic thermal estimationLove Singhal, Sejong Oh, Eli Bozorgzadeh. 67-70 [doi]
- Reconfigurable RTD-based circuit elements of complete logic functionalityYexin Zheng, Chao Huang. 71-76 [doi]
- MBARC: A scalable memory based reconfigurable computing framework for nanoscale devicesSomnath Paul, Swarup Bhunia. 77-82 [doi]
- Moving forward: A non-search based synthesis method toward efficient CNOT-based quantum circuit synthesis algorithmsMehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi. 83-88 [doi]
- A CAD tool for RF MEMS devicesRajesh Pande, Rajendra Patrikar. 89-94 [doi]
- A 1.2GHz delayed clock generator for high-speed microprocessorsInhwa Jung, Moo-young Kim, Chulwoo Kim. 95-96 [doi]
- LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS processAkiko Mineyama, Hiroyuki Ito, Takahiro Ishii, Kenichi Okada, Kazuya Masu. 97-98 [doi]
- A slew-rate controlled output driver with one-cycle tuning timeYoung-Ho Kwak, Inhwa Jung, Chulwoo Kim. 99-100 [doi]
- A low-leakage current power 180-nm CMOS SRAMTadayoshi Enomoto, Yuki Higuchi. 101-102 [doi]
- A CMOS direct sampling mixer using Switched Capacitor Filter technique for software-defined radioHong Phuc Ninh, Takashi Moue, Takashi Kurashina, Kenichi Okada, Akira Matsuzawa. 103-104 [doi]
- Small-area CMOS RF distributed mixer using multi-port inductorsSusumu Sadoshima, Satoshi Fukuda, Tackya Yammouch, Hiroyuki Ito, Kenichi Okada, Kazuya Masu. 105-106 [doi]
- Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verificationYasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye. 107-108 [doi]
- Duo-binary circular turbo decoder based on border metric encoding for WiMAXJi-Hoon Kim, In-Cheol Park. 109-110 [doi]
- Area and power efficient design of coarse time synchronizer and frequency offset estimator for fixed WiMAX systemsTae-Hwan Kim, In-Cheol Park. 111-112 [doi]
- A low-cost cryptographic processor for security embedded systemRonghua Lu, Jun Han, Xiaoyang Zeng, Qing Li, Lang Mai, Jia Zhao. 113-114 [doi]
- Multithreaded coprocessor interface for multi-core multimedia SoCShih-Hao Ou, Tay-Jyi Lin, Xiang Sheng Deng, Zhi Hong Zhuo, Chih-Wei Liu. 115-116 [doi]
- Parameterized embedded in-circuit emulator and its retargetable debugging software for microprocessor/microcontroller/DSP processorLiang-Bi Chen, Yung-Chih Liu, Chen-Hung Chen, Chung-Fu Kao, Ing-Jer Huang. 117-118 [doi]
- Global optimization of common subexpressions for multiplierless synthesis of multiple constant multiplicationsYuen-Hong Alvin Ho, Chi-Un Lei, Hing-Kit Kwan, Ngai Wong. 119-124 [doi]
- Decomposition based approach for synthesis of multi-level threshold logic circuitsTejaswi Gowda, Sarma B. K. Vrudhula. 125-130 [doi]
- Timing-power optimization for mixed-radix Ling adders by integer linear programmingYi Zhu, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng. 131-137 [doi]
- Efficient synthesis of compressor trees on FPGAsHadi Parandeh-Afshar, Philip Brisk, Paolo Ienne. 138-143 [doi]
- Area recovery under depth constraint by Cut Substitution for technology mapping for LUT-based FPGAsTaiga Takata, Yusuke Matsunaga. 144-147 [doi]
- An optimal algorithm for sizing sequential circuits for industrial library based designsSanghamitra Roy, Yu Hen Hu, Charlie Chung-Ping Chen, Shih-Pin Hung, Tse-Yu Chiang, Jiuan-Guei Tseng. 148-151 [doi]
- Efficient numerical modeling of random rough surface effects for interconnect internal impedance extractionQuan Chen, Ngai Wong. 152-157 [doi]
- Efficient techniques for 3-D impedance extraction using mixed boundary element methodFang Gong, Wenjian Yu, Zeyi Wang, Zhiping Yu, Changhao Yan. 158-163 [doi]
- Generating stable and sparse reluctance/inductance matrix under insufficient conditionsYuichi Tanji, Takayuki Watanabe, Hideki Asai. 164-169 [doi]
- Hierarchical Krylov subspace reduced order modeling of large RLC circuitsDuo Li, Sheldon X.-D. Tan. 170-175 [doi]
- Statistical noise margin estimation for sub-threshold combinational circuitsYu Pu, Jose de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha. 176-179 [doi]
- Symmetry-aware placement with transitive closure graphs for analog layout designLihong Zhang, C.-J. Richard Shi, Yingtao Jiang. 180-185 [doi]
- Constraint-free analog placement with topological symmetry structureQing Dong, Shigetoshi Nakatake. 186-191 [doi]
- TCG-based multi-bend bus driven floorplanningTilen Ma, Evangeline F. Y. Young. 192-197 [doi]
- Large-scale fixed-outline floorplanning design using convex optimization techniquesChaomin Luo, Miguel F. Anjos, Anthony Vannelli. 198-203 [doi]
- Bus-aware microarchitectural floorplanningDae-Hyun Kim, Sung Kyu Lim. 204-208 [doi]
- LP based white space redistribution for thermal via planning and performance optimization in 3D ICsXin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong. 209-212 [doi]
- Predictive models and CAD methodology for pattern dependent variabilityNishath Verghese, Richard Rouse, Philippe Hurat. 213-218 [doi]
- Technology modeling and characterization beyond the 45nm nodeSani R. Nassif. 219 [doi]
- Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyondDavid Z. Pan, Minsik Cho. 220-225 [doi]
- MaizeRouter: Engineering an effective global routerMichael D. Moffitt. 226-231 [doi]
- A new global router for modern designsJhih-Rong Gao, Pei-Ci Wu, Ting-Chi Wang. 232-237 [doi]
- Routability driven modification method of monotonic via assignment for 2-layer Ball Grid Array packagesYoichi Tomioka, Atsushi Takahashi. 238-243 [doi]
- Ordered escape routing based on Boolean satisfiabilityLijuan Luo, Martin D. F. Wong. 244-249 [doi]
- MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networksAnand Rajaram, David Z. Pan. 250-257 [doi]
- Interconnect modeling for improved system-level design optimizationLuca P. Carloni, Andrew B. Kahng, Swamy Muddu, Alessandro Pinto, Kambiz Samadi, Puneet Sharma. 258-264 [doi]
- NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networksJeremy Chan, Sri Parameswaran. 265-270 [doi]
- Automatic generation of hardware dependent software for MPSoCs from abstract system specificationsGunar Schirner, Andreas Gerstlauer, Rainer Dömer. 271-276 [doi]
- Application-specific Network-on-Chip architecture synthesis based on set partitions and Steiner TreesShan Yan, Bill Lin. 277-282 [doi]
- Floating-point reconfiguration array processor for 3D graphics physics engineHoonmo Yang. 283 [doi]
- Super-K: A SoC for single-chip ultra mobile computerXu Cheng. 284 [doi]
- The evolution of SoC platform according to the new mobile paradigmKi-Soo Hwang. 285 [doi]
- Statistical gate delay model for Multiple Input SwitchingTakayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera. 286-291 [doi]
- Non-Gaussian Statistical Timing models of die-to-die and within-die parameter variations for full chip analysisKatsumi Homma, Izumi Nitta, Toshiyuki Shibuya. 292-297 [doi]
- Non-Gaussian statistical timing analysis using second-order polynomial fittingLeronq Cheng, Jinjun Xiong, Lei He. 298-303 [doi]
- A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in UDVS applicationSaihua Lin, Yu Wang, Rong Luo, Huazhong Yang. 304-309 [doi]
- Static timing: Back to our rootsRuiming Chen, Lizheng Zhang, Vladimir Zolotov, Chandu Visweswariah, Jinjun Xiong. 310-315 [doi]
- Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block selection algorithmJui-Yuan Hsieh, Shanq-Jang Ruan. 316-321 [doi]
- Block cache for embedded systemsDominic Hillenbrand, Jörg Henkel. 322-327 [doi]
- A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architecturesAviral Shrivastava, Ilya Issenin, Nikil Dutt. 328-333 [doi]
- Fast, quasi-optimal, and pipelined instruction-set extensionsAjay K. Verma, Philip Brisk, Paolo Ienne. 334-339 [doi]
- Load scheduling: Reducing pressure on distributed register files for freeMei Wen, Nan Wu, Maolin Guan, Chunyuan Zhang. 340-345 [doi]
- DPlace2.0: A stable and efficient analytical placement based on diffusionTao Luo, David Z. Pan. 346-351 [doi]
- Total power optimization combining placement, sizing and multi-Vt through slack distribution managementTao Luo, David Newmark, David Z. Pan. 352-357 [doi]
- An innovative Steiner tree based approach for polygon partitioningYongqiang Lu, Qing Su, Jamil Kawa. 358-363 [doi]
- An MILP-based wire spreading algorithm for PSM-aware layout modificationMing-Chao Tsai, Yung-Chia Lin, Ting-Chi Wang. 364-369 [doi]
- Low power clock buffer planning methodology in F-D placement for large scale circuit designYanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian. 370-375 [doi]
- Power grid analysis benchmarksSani R. Nassif. 376-381 [doi]
- In-band mobile digital TV transmission technology for advanced television systems committeeJunehee Lee. 382 [doi]
- In-vehicle vision processors for driver assistance systemsShorin Kyo, Shin ichiro Okazaki. 383-388 [doi]
- Multi-core DSP for base stations: Large and smallDoug Pulley. 389-391 [doi]
- 1-cc computer using UWB-IR for wireless sensor networkTatsuo Nakagawa, Masayuki Miyazaki, Goichi Ono, Ryosuke Fujiwara, Takayasu Norimatsu, Takahide Terada, Akira Maeki, Yuji Ogata, Shinsuke Kobayashi, Noboru Koshizuka, Ken Sakamura. 392-397 [doi]
- Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proofUdo Krautz, Markus Wedler, Wolfgang Kunz, Kai Weber, Christian Jacobi 0002, Matthias Pflanz. 398-403 [doi]
- A symbolic approach for mixed-signal model checkingAlexander Jesser, Lars Hedrich. 404-409 [doi]
- Faster projection based methods for circuit level verificationChao Yan, Mark R. Greenstreet. 410-415 [doi]
- A debug probe for concurrently debugging multiple embedded cores and inter-core transactions in NoC-based systemsShan Tang, Qiang Xu. 416-421 [doi]
- A fast two-pass HDL simulation with on-demand dumpKyuho Shim, Youngrae Cho, Namdo Kim, Hyuncheol Baik, Kyungkuk Kim, Dusung Kim, Jaebum Kim, Byeongun Min, Kyumyung Choi, Maciej J. Ciesielski, Seiyang Yang. 422-427 [doi]
- Hybrid solid-state disks: Combining heterogeneous NAND flash in large SSDsLi-Pin Chang. 428-433 [doi]
- Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata informationAlexandros Bartzas, Miguel Peon-Quiros, Stylianos Mamagkakis, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias. 434-439 [doi]
- Automatic re-coding of reference code into structured and analyzable SoC modelsPramod Chandraiah, Rainer Dömer. 440-445 [doi]
- Action coverage formulation for power optimization in body sensor networksHassan Ghasemzadeh, Eric Guenterberg, Katherine Gilani, Roozbeh Jafari. 446-451 [doi]
- Dynamic scheduling of imprecise-computation tasks in maximizing QoS under energy constraints for embedded systemsHeng Yu, Bharadwaj Veeravalli, Yajun Ha. 452-455 [doi]
- Architecture-level thermal behavioral characterization for multi-core microprocessorsDuo Li, Sheldon X.-D. Tan, Murli Tirumala. 456-461 [doi]
- Full-chip thermal analysis for the early design stage via generalized integral transformsPei-Yu Huang, Chih-Kang Lin, Yu-Min Lee. 462-467 [doi]
- A stochastic local hot spot alerting techniqueHwisung Jung, Massoud Pedram. 468-473 [doi]
- Design rule optimization of regular layout for leakage reduction in nanoscale designAnupama R. Subramaniam, Ritu Singhal, Chi-Chao Wang, Yu Cao. 474-479 [doi]
- Investigation of diffusion rounding for post-lithography analysisPuneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester. 480-485 [doi]
- Pessimism reduction in coupling-aware static timing analysis using timing and logic filteringDebasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou. 486-491 [doi]
- A fast incremental clock skew scheduling algorithm for slack optimizationKui Wang, Hao Fang, Hu Xu, Xu Cheng. 492-497 [doi]
- Clock tree synthesis with data-path sensitivity matchingMatthew R. Guthaus, Dennis Sylvester, Richard B. Brown. 498-503 [doi]
- Buffered clock tree synthesis for 3D ICs under thermal variationsJacob R. Minz, Xin Zhao, Sung Kyu Lim. 504-509 [doi]
- A delay model for interconnect trees based on ABCD matrixGuofei Zhou, Li Su, Depeng Jin, Lieguang Zeng. 510-513 [doi]
- Analytical model for the impact of multiple input switching noise on timingRajeshwary Tayade, Sani R. Nassif, Jacob A. Abraham. 514-517 [doi]
- Determination of optimal polynomial regression function to decompose on-die systematic and random variationsTakashi Sato, Hiroyuki Ueyama, Noriaki Nakayama, Kazuya Masu. 518-523 [doi]
- Within-die process variations: How accurately can they be statistically modeled?Brendan Hargreaves, Henrik Hult, Sherief Reda. 524-530 [doi]
- Chebyshev Affine Arithmetic based parametric yield prediction under limited descriptions of uncertaintyJin Sun, Yue Huang, Jun Li, Janet Meiling Wang. 531-536 [doi]
- Distribution arithmetic for stochastical analysisMarkus Olbrich, Erich Barke. 537-542 [doi]
- Handling partial correlations in yield predictionSridhar Varadan, Janet Meiling Wang, Jiang Hu. 543-548 [doi]
- Reliability-aware design for nanometer-scale devicesDavid Atienza, Giovanni De Micheli, Luca Benini, José L. Ayala, Pablo Garcia Del Valle, Michael DeBole, Vijay Narayanan. 549-554 [doi]
- An industrial perspective of power-aware reliable SoC designSoo-Kwan Eo, Sungjoo Yoo, Kyu-Myung Choi. 555-557 [doi]
- The future of semiconductor industry - A foundry s perspectiveF. C. Tseng. 558 [doi]
- Soft error rate reduction using redundancy addition and removalKai-Chiang Wu, Diana Marculescu. 559-564 [doi]
- Localized random access scan: Towards low area and routing overheadYu Hu, Xiang Fu, Xiaoxin Fan, Hideo Fujiwara. 565-570 [doi]
- A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faultsFei Wang, Yu Hu, Huawei Li, Xiaowei Li. 571-576 [doi]
- GECOM: Test data compression combined with all unknown response maskingYouhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki. 577-582 [doi]
- Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switchesMinje Jun, Sungjoo Yoo, Eui-Young Chung. 583-588 [doi]
- Automatic interface synthesis based on the classification of interface protocols of IPsChangRyul Yun, Dongsoo Kang, Younghwan Bae, Hanhn Cho, KyoungSon Jhang. 589-594 [doi]
- The Shining embedded system design methodology based on self dynamic reconfigurable architecturesCarlo Curino, Luca Fossati, Vincenzo Rana, Francesco Redaelli, Marco D. Santambrogio, Donatella Sciuto. 595-600 [doi]
- Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrivalSujan Pandey, Rolf Drechsler. 601-606 [doi]
- A Multi-Processor NoC platform applied on the 802.11i TKIP cryptosystemJung-Ho Lee, Sung-Rok Yoon, Kwang-Eui Pyun, Sin-Chong Park. 607-610 [doi]
- A unified methodology for power supply noise reduction in modern microarchitecture designMichael B. Healy, Fayez Mohamood, Hsien-Hsin S. Lee, Sung Kyu Lim. 611-616 [doi]
- Heuristic power/ground network and floorplan co-design methodXiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong. 617-622 [doi]
- Vertical via design techniques for multi-layered P/G networksShuai Li, Jin Shi, Yici Cai, Xianlong Hong. 623-628 [doi]
- Statistical mixed Vt allocation of body-biased circuits for reduced leakage variationJinseob Jeong, Seungwhun Paik, Youngsoo Shin. 629-634 [doi]
- Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretchingSwaroop Ghosh, Kaushik Roy. 635-640 [doi]
- Circuit lines for guiding the generation of random test sequences for synchronous sequential circuitsIrith Pomeranz, Sudhakar M. Reddy. 641-646 [doi]
- A new low energy BIST using a statistical codeSunghoon Chun, Taejin Kim, Sungho Kang. 647-652 [doi]
- On reducing both shift and capture power for scan-based testingJia Li, Qiang Xu, Yu Hu, Xiaowei Li. 653-658 [doi]
- Robust test generation for power supply noise induced path delay faultsXiang Fu, Huawei Li, Yu Hu, Xiaowei Li. 659-662 [doi]
- Test vector chains for increased targeted and untargeted fault coverageIrith Pomeranz, Sudhakar M. Reddy. 663-666 [doi]
- Parallel fault backtracing for calculation of fault coverageRaimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman. 667-672 [doi]
- ReSP: A non-intrusive Transaction-Level Reflective MPSoC Simulation Platform for design space explorationGiovanni Beltrame, Cristiana Bolchini, Luca Fossati, Antonio Miele, Donatella Sciuto. 673-678 [doi]
- Collaborative hardware/software partition of coarse-grained reconfigurable system using evolutionary ant colony optimizationDawei Wang, Sikun Li, Yong Dou. 679-684 [doi]
- Design space exploration for a coarse grain acceleratorFarhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami. 685-690 [doi]
- Efficient symbolic multi-objective design space explorationMartin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich. 691-696 [doi]
- Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2:::n:::)Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki. 697-702 [doi]
- Optimal allocation and placement of thermal sensors for reconfigurable systems and its practical extensionByungHyun Lee, Taewhan Kim. 703-707 [doi]
- Exploring power management in multi-core systemsReinaldo A. Bergamaschi, Guoling Han, Alper Buyuktosunoglu, Hiren D. Patel, Indira Nair, Gero Dittmann, Geert Janssen, Nagu R. Dhanwada, Zhigang Hu, Pradip Bose, John A. Darringer. 708-713 [doi]
- Dependability, power, and performance trade-off on a multicore processorToshinori Sato, Toshimasa Funaki. 714-719 [doi]
- High performance current-mode differential logicLing Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng, Masanori Hashimoto. 720-725 [doi]
- NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?Kunhyuk Kang, Saakshi Gangwal, Sang Phill Park, Kaushik Roy. 726-731 [doi]
- Reaching the limits of low power designJ. S. Hobbs, T. W. Williams. 732-735 [doi]
- Software-cooperative power-efficient heterogeneous multi-core for media processingHiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara. 736-741 [doi]
- Experiences of low power design implementation and verificationShi-Hao Chen, Jiing-Yuan Lin. 742-747 [doi]
- Low power architecture and design techniques for mobile handset LSI Medity:::TM::: M2Shuichi Kunie, Takefumi Hiraga, Tatsuya Tokue, Sunao Torii, Taku Ohsawa. 748-753 [doi]
- An efficient, fully nonlinear, variability-aware non-monte-carlo yield estimation procedure with applications to SRAM cells and ring oscillatorsChenjie Gu, Jaijeet S. Roychowdhury. 754-761 [doi]
- Analog circuit simulation using range arithmeticsDarius Grabowski, Markus Olbrich, Erich Barke. 762-767 [doi]
- LTCC spiral inductor modeling, synthesis, and optimizationTuck Boon Chan, Hsin-Chia Lu, Jun-Kuei Zeng, Charlie Chung-Ping Chen. 768-771 [doi]
- Symmetry constraint based on mismatch analysis for analog layout in SOI technologyJiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto. 772-775 [doi]
- SPKM : A novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architecturesJonghee W. Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Reiley Jeyapaul, Yunheung Paek. 776-782 [doi]
- Block remap with turnoff: A variation-tolerant cache design techniqueMohammed Abid Hussain, Madhu Mutyam. 783-788 [doi]
- ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chipSudeep Pasricha, Nikil Dutt. 789-794 [doi]
- Webpage-based benchmarks for mobile device designMarc Somers, JoAnn M. Paul. 795-800 [doi]
- Panel: Best ways to use billions of devices on a chipGrant Martin. 801-802 [doi]
- VEBoC: Variation and error-aware design for billions of devices on a chipShoaib Akram, Scott Cromar, Gregory Lucas, Alexandros Papakonstantinou, Deming Chen. 803-808 [doi]
- Quo vadis, BTSoC (Billion Transistor SoC)?Nikil Dutt. 809 [doi]
- Best ways to use billions of devices on a wireless mobile SoCKyungHo Kim. 810 [doi]
- Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designsKazutoshi Kobayashi, Hidetoshi Onodera. 811-812 [doi]