Table of Contents

• The hype, myths, and realities of testing 2.5D/3D integrated circuitsKrishnendu Chakrabarty. 1 [doi]
• Known unknowns - Knowledge in the presence of unknownsBernd Becker. 1 [doi]
• Accessing on-chip instruments through the life-time of systemsErik Larsson, Farrokh Ghani Zadegan. 2-4 [doi]
• Transforming nanodevices into nanosystems: The N3XT 1, 000XSubhasish Mitra. 6 [doi]
• Spin transfer torque memories for on-chip caches: Prospects and perspectivesAkhilesh Jaiswal, Kaushik Roy. 7 [doi]
• Proposal of a functional safety methodology applied to fault tolerance in FPGA applicationsBruna F. Flesch, Bianca Brand, Rodrigo Marques de Figueiredo, Lucio Rene Prade, Marcio Rosa da Silva. 8-13 [doi]
• Analysis of the effects of soft errors on compression algorithms through fault injection inside program variablesSerhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Görschwin Fey. 14-19 [doi]
• A comprehensive approach to fault tolerance: Device, circuit, and system techniquesZoran Stamenkovic, Vladimir Petrovic. 20 [doi]
• Auxiliary IP blocks for early dependability analysis of small processor based systemsJ. Barboza, J. Basualdo, J. Perez Acle. 21-26 [doi]
• Dependability evaluation of COTS microprocessors via on-chip debugging facilitiesJose Isaza-Gonzalez, Alejandro Serrano-Cases, Felipe Restrepo-Calle, Sergio Cuenca-Asensi, Antonio Martínez-Álvarez. 27-32 [doi]
• A comprehensive software-based self-test and self-repair method for statically scheduled superscalar processorsMario Schölzel, Tobias Koal, Sebastian Müller, Stefan Scharoba, Stephanie Roder, Heinrich Theodor Vierhaus. 33-38 [doi]
• A probabilistic model for stuck-on faults in combinational logic gatesRafael B. Schivittz, Denis T. Franco, Cristina Meinhardt, Paulo F. Butzen. 39-44 [doi]
• Fault model qualification by assertion miningAlessandro Danese, Jacopo Mocci, Graziano Pravadelli. 45-50 [doi]
• A control path aware metric for grading functional test vectorsKelson Gent, Michael S. Hsiao. 51-56 [doi]
• On the consolidation of mixed criticalities applications on multicore architecturesStefano Esposito, Sehriy Avramenko, Massimo Violante. 57-62 [doi]
• Using traffic monitoring to tolerate multiple faults in 3D NoCsAnelise Kologeski, Henrique Colao Zanuz, Fernanda Lima Kastensmidt. 63-68 [doi]
• On-line fault classification and handling in IEEE1687 based fault management system for complex SoCsKonstantin Shibin, Sergei Devadze, Artur Jutman. 69-74 [doi]
• Gate-level modelling of NBTI-induced delays under process variationsThiago Copetti, Guilherme Medeiros, Leticia Bolzani Poehls, Fabian Vargas, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Raimund Ubar. 75-80 [doi]
• A methodology for NBTI circuit reliability at reduced power consumption using dual supply voltageFreddy Forero, Andres Gomez, Victor H. Champac. 81-86 [doi]
• Analyzing NBTI impact on SRAMs with resistive-open defectsM. Tulio Martins, G. Cardoso Medeiros, Thiago Copetti, Fabian Vargas, Letícia Maria Bolzani Poehls. 87-92 [doi]
• Evaluating the effects of single event upsets in soft-core GPGPUsWerner Nedel, Fernanda Lima Kastensmidt, José Rodrigo Azambuja. 93-98 [doi]
• Hybrid soft error mitigation techniques for COTS processor-based systemsEduardo Chielle, Boyang Du, Fernanda Lima Kastensmidt, Sergio Cuenca-Asensi, Luca Sterpone, Matteo Sonza Reorda. 99-104 [doi]
• Attacking the smart grid using public informationCharalambos Konstantinou, Marios Sazos, Michail Maniatakos. 105-110 [doi]
• Radiation effects in low power and ultra low power voltage referencesDaniel Fusco, Tiago R. Balen. 111-116 [doi]
• Fault simulation in radiation-hardened SOI CMOS VLSIs using universal compact MOSFET modelKonstantin O. Petrosyants, Lev M. Sambursky, Igor A. Kharitonov, Boris G. Lvov. 117-122 [doi]
• Performance evaluation of radiation hardened analog circuits based on Enclosed Layout geometryGuilherme S. Cardoso, Tiago R. Balen. 123-128 [doi]
• Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defectAmit Karel, Mariane Comte, Jean Marc Gallière, Florence Azaïs, Michel Renovell. 129-134 [doi]
• On-silicon validation of a benchmark generation methodology for effectively evaluating combinational cell library designM. De Carvalho, M. Altieri, L. Puricelli, Renato P. Butzen, Renato P. Ribas, Eric E. Fabris. 135-140 [doi]
• A methodology for early functional verification of embedded software combining virtual platforms and bounded model checkingRogerio Paludo, Djones Lettnin. 141-146 [doi]
• Soft error analysis in embedded software developed with & without operating systemLuiz Gustavo Casagrande, Fernanda Lima Kastensmidt. 147-152 [doi]
• A HW-dependent software model for cross-layer fault analysis in embedded systemsChristian Bartsch, Nico Rödel, Carlos Villarraga, Dominik Stoffel, Wolfgang Kunz. 153-158 [doi]
• A SystemC-based platform for assertion-based verification and mutation analysis in systems biologyDaniele Coati, Rosario Distefano, Nicola Bombieri, Franco Fummi, Michela Mirenda, Carlo Laudanna, Rosalba Giugno. 159-164 [doi]
• Infrastructure for formal and dynamic verification of peripheral programming modelWalter Soto Encinas, Francisco Romulo da Silva Araujo, Harney Abrahim. 165-170 [doi]
• System-level diagnosis for WSN: A heuristicMauricio de Oliveira Barros, Andrea Weber. 171-176 [doi]
• On automatic software-based self-test program generation based on high-level decision diagramsArtjom Jasnetski, Raimund Ubar, Anton Tsertov. 177 [doi]
• A deep analysis of SEU consequences in the internal memory of LEON3 processorAfef Kchaou, W. El Hadj Youssef, Rached Tourki, Fraidy Bouesse, Pablo Ramos, Raoul Velazco. 178 [doi]
• Soft error analysis at sequential and parallel applications in ARM Cortex-A9 dual-coreGennaro Severino Rodrigues, Fernanda Lima Kastensmidt. 179 [doi]
• Reliability analysis of majority voters under permanent faultsEduardo Liebl, Cristina Meinhardt, Paulo F. Butzen. 180 [doi]
• Single Trojan injection model generation and detectionHarini Bhamidipati, Daniel G. Saab, Jacob A. Abraham. 181 [doi]
• Checksum based error detection in linearized representations of non linear control systemsSuvadeep Banerjee, Abhijit Chatterjee, Jacob A. Abraham. 182 [doi]
• Dependable on-chip infrastructure for dependable MPSOCsMichael A. Kochte, Hans-Joachim Wunderlich. 183-188 [doi]
• A layered approach for fault tolerant NoC-based MPSoCs - Special session: Dependable MPSoCsEduardo Wächter, Francisco F. S. Barreto, Vinicius Fochi, Alexandre M. Amory, Fernando Gehm Moraes. 189-194 [doi]
• Three-Independent-Gate Transistors: Opportunities in digital, analog and RF applicationsPierre-Emmanuel Gaillardon, Romain Magni, Luca Gaetano Amarù, Mehdi Hasan, Ross Walker, Berardi Sensale-Rodriguez, Jean-Frédéric Christmann, Edith Beigné. 195-200 [doi]