Table of Contents

• RC-IJTAG: A Methodology for Designing Remotely-Controlled IEEE 1687 Scan NetworksPayam Habiby, Sebastian Huhn 0001, Rolf Drechsler. 1-6 [doi]
• QuardTropy: Detecting and Quantifying Unauthorized Information Leakage in Hardware Designs using g-entropyHasan Al Shaikh, Mohammad Bin Monjil, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor, Fahim Rahman. 1-6 [doi]
• Simulation Methodology for Assessing X-Ray Effects on Digital CircuitsNasr-Eddine Ouldei Tebina, Nacer-Eddine Zergainoh, Guillaume Hubert, Paolo Maistri. 1-6 [doi]
• An Efficient Security Closure Methodology for EM-based Attacks on Power Grid StructuresAlexandra Takou, Pavlos Stoikos, Moysis Moysis, George Floros 0002, Nestoras E. Evmorfopoulos, Georgios I. Stamoulis. 1-4 [doi]
• Highly Efficient Layered Syndrome-based Double Error Correction Utilizing Current Summing in RRAM Cells to Simplify DecoderShruti Dutta, Sai Charan Rachamadugu Chinni, Abhishek Das, Nur A. Touba. 1-4 [doi]
• Gradient Descent Iterative Correction Unit for Fixed Point Parity Based CodesOana Boncalo, Alexandru Amaricai. 1-4 [doi]
• Analyzing the Reliability of Alternative Convolution Implementations for Deep Learning ApplicationsCristiana Bolchini, Luca Cassano, Antonio Miele, Alessandro Nazzari, Dario Passarello. 1-6 [doi]
• Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-TestabilityJin-Fu Li. 1-6 [doi]
• An efficient High-Volume Production Performance Screening using On-Chip Ring OscillatorsTobias Kilian, Abhishek Sengupta, Daniel Tille, Martin Huch, Ulf Schlichtmann. 1-6 [doi]
• Testing and Reliability of Spiking Neural Networks: A Review of the State-of-the-ArtHaralampos-G. Stratigopoulos, Theofilos Spyrou, Spyridon Raptis. 1-8 [doi]
• Analysis and Improvement of Resilience for Long Short-Term Memory Neural NetworksMohammad Hasan Ahmadilivani, Jaan Raik, Masoud Daneshtalab, Alar Kuusik. 1-4 [doi]
• Challenges in Machine Learning Techniques to Estimate Reliability from Transistors to CircuitsVictor M. van Santen, Florian Klemme, Paul R. Genssler, Hussam Amrouch. 1-6 [doi]
• X ray nanoprobe for fault attacks and circuit edits on 28-nm integrated circuitsS. Bouat, Stéphanie Anceau, Laurent Maingault, Jessy Clédière, Luc Salvo, Rémi Tucoulou. 1-6 [doi]
• Image Degradation in Time Due to Interacting Hot PixelsGlenn H. Chapman, Klinsmann J. Coelho Silva Meneses, Linda Wu, Israel Koren, Zahava Koren. 1-6 [doi]
• Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing AnalysisChristos Georgakidis, Dimitris Valiantzas, Stavros Simoglou, Iordanis Lilitsis, Nikolaos Chatzivangelis, Ilias Golfos, Marko S. Andjelkovic, Christos P. Sotiriou, Milos Krstic. 1-6 [doi]
• Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming CodesAlessandro Palumbo, Luca Cassano, Pedro Reviriego, Marco Ottavi. 1-6 [doi]
• Neutron Radiation Tests of the NEORV32 RISC-V SoC on Flash-Based FPGAsKevin Böhmer, Bruno Forlin, Carlo Cazzaniga, Paolo Rech, Gianluca Furano, Nikolaos Alachiotis 0001, Marco Ottavi. 1-6 [doi]
• On the Prediction of Hardware Security Properties of HLS Designs Using Graph Neural NetworksAmalia-Artemis Koufopoulou, Athanasios Papadimitriou, Aggelos Pikrakis, Mihalis Psarakis, David Hély. 1-6 [doi]
• Implementation and Reliability Evaluation of a RISC-V Vector Extension UnitCarolina Imianosky, Douglas A. dos Santos, Douglas R. Melo, Felipe Viel, Luigi Dilillo. 1-6 [doi]
• SASL-JTAG: A Light-Weight Dependable JTAGSenling Wang, Shaoqi Wei, Jun Ma, Hiroshi Kai, Yoshinobu Higami, Hiroshi Takahashi, Akihiro Shimizu, Xiaoqing Wen, Tianming Ni. 1-3 [doi]
• Iterative Mitigation of Insecure Resource Sharing Produced by High-level SynthesisZahin Ibnat, Hadi Mardani Kamali, Farimah Farahmandi. 1-6 [doi]
• Exploration of System-on-Chip Secure-Boot Vulnerability to Fault-Injection by Side-Channel AnalysisClément Fanjas, Driss Aboulkassimi, Simon Pontié, Jessy Clédière. 1-6 [doi]
• An Estimation Method of Defect Types Using Artificial Neural Networks and Fault Detection InformationNatsuki Ota, Toshinori Hosokawa, Koji Yamazaki, Yukari Yamauchi, Masayuki Arai. 1-6 [doi]
• Accurate Soft Error Rate Evaluation Using Event-Driven Dynamic Timing AnalysisGeorgios Ioannis Paliaroutis, Pelopidas Tsoumanis, Dimitrios Garyfallou, Anastasis Vagenas, Nestoras E. Evmorfopoulos, Georgios I. Stamoulis. 1-6 [doi]
• Reliability of Computing-In-Memories: Threats, Detection Methods, and Mitigation ApproachesYu-Guang Chen, Ying-Jing Tsai. 1-6 [doi]
• On Attacking Scan-based Logic Locking SchemesGovind Rajhans Jadhav, Sonali Shukla, Virendra Singh. 1-4 [doi]
• Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan HorsesAlessandro Palumbo, Marco Ottavi, Luca Cassano. 1-6 [doi]
• A Low-Cost Hardware Accelerator for CCSDS 123 Lossless Hyperspectral Image CompressionWesley Grignani, Douglas A. dos Santos, Luigi Dilillo, Felipe Viel, Douglas R. Melo. 1-6 [doi]
• Evaluating the Impact of Aging on Path-Delay Self-Test LibrariesRiccardo Cantoro, Sandro Sartoni, Matteo Sonza Reorda, Lorena Anghel, Michele Portolan. 1-7 [doi]
• Investigating the effect of approximate multipliers on the resilience of a systolic array DNN acceleratorSalvatore Pappalardo, Ali Piri, Annachiara Ruospo, Ian O'Connor, Bastien Deveautour, Ernesto Sánchez 0001, Alberto Bosio. 1-6 [doi]
• Fault Secured JPEG-Codec Hardware Accelerator with Piracy Detective Control using Secure Fingerprint TemplateRahul Chaurasia, Abhinav Reddy Asireddy, Anirban Sengupta. 1-6 [doi]
• On-Chip Sensors Data Collection and Analysis for SoC Health ManagementKonstantin Shibin, Maksim Jenihhin, Artur Jutman, Sergei Devadze, Anton Tsertov. 1-6 [doi]
• Hardening a Real-Time Operating System for a Dependable RISC-V System-on-ChipBenjamin W. Mezger, Douglas A. dos Santos, Luigi Dilillo, Douglas R. Melo. 1-6 [doi]
• Characterization of a Fault-Tolerant RISC-V System-on-Chip for Space EnvironmentsDouglas A. dos Santos, André Martins Pio de Mattos, Douglas R. Melo, Luigi Dilillo. 1-6 [doi]
• Partial Triple Modular Redundancy Method for Fault-Tolerant Circuit based on HITS AlgorithmYu Xie, Wen-Yue Yu, Ning Zhang, He Chen, Yizhuang Xie. 1-4 [doi]
• On the resilience of representative and novel data formats in CNNsGabriele Gavarini, Annachiara Ruospo, Ernesto Sánchez 0001. 1-6 [doi]
• DDSR: An Online GPGPU Instruction Decoder Error Detecting and Correcting ArchitectureRaghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh. 1-6 [doi]
• Uncovering hidden vulnerabilities in CNNs through evolutionary-based Image Test LibrariesV. Turco, Annachiara Ruospo, Gabriele Gavarini, Ernesto Sánchez 0001, Matteo Sonza Reorda. 1-6 [doi]
• Black-Box IP Validation with the SafeTI Traffic Injector: A Success StoryFrancisco Fuentes, Sergi Alcaide, Raimon Casanova, Jaume Abella 0001. 1-4 [doi]
• A Block Partitioning Method for Region Exhaustive Test to Reduce the Number of Test Patterns and Improve Gate Exhaustive Fault CoverageMomona Mizota, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai. 1-6 [doi]
• An Evaluation of a Testability Measure for State Assignment to Estimate Transition Fault Coverage for ControllersToshinori Hosokawa, Kyohei Iizuka, Masayoshi Yoshimura. 1-6 [doi]
• EnSAFe: Enabling Sustainable SoC Security Auditing using eFPGA-based AcceleratorsMridha Md Mashahedur Rahman, Shams Tarek, Kimia Zamiri Azar, Farimah Farahmandi. 1-6 [doi]
• An Evaluation of Estimated Field Random Testability for Data Paths at Register Transfer Level Using Status Signal Sequences Based on k-Consecutive State Transitions for Field TestingYudai Toyooka, Haruki Watanabe, Toshinori Hosokawa, Masayoshi Yoshimura. 1-6 [doi]
• Hardware Trojans of Computing-In-Memories: Issues and MethodsShih-Hsu Huang, Wei-Che Cheng, Jin-Fu Li 0001. 1-6 [doi]
• A Machine Learning-driven EDAC Method for Space-Application MemoryJunchao Chen 0001, Marko S. Andjelkovic, Milos Krstic, Fabian Luis Vargas 0001. 1-6 [doi]
• A Self Aware Security Approach for Real Time Neural Network Applications from Row Hammer Attacks in Multi FPGA Multi User EnvironmentKrishnendu Guha, Gouriprasad Bhattacharyya. 1-4 [doi]