Abstract is missing.
- Improved Fault Detection Using a Charge MonitorRodrigo Picos, Oscar Calvo, Miquel Roca, Eugenio García Moreno, Miron Abramovici. 19-24
- Using Swarm Intelligence to Solve Some Analog Test IssuesC. E. F. Savioli, C. E. C. Szendrodi, José Vicente Calvano, Antonio Carneiro de Mesquita Filho. 25-29
- Cube Subtraction in SAT SolversRomanelli Lodron Zuim, José T. Souza, Claudionor José Nunes Coelho Jr.. 33-38
- Oscillation-based Test in Digital IIR FiltersGabriela Peretti, Eduardo Romero 0002, Carlos A. Marqués. 41-46
- Concurrent Testing of Digital Circuits for Non-Classical Fault Models: Bridging Faults and n-Detect TestSantosh Biswas, Amit Patra, Siddhartha Mukhopadhyay. 49-54
- BIST Architectures and Fault EmulationAbilio Parreira, Marcelino B. Santos, João Paulo Teixeira 0001. 55-60
- Scan Pattern WatermarkingDavid Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. 63-67
- A Fault Injection Environment for SoPC's Embedded MicroprocessorsMarta Portela-García, Luca Sterpone, Matteo Sonza Reorda, Massimo Violante. 68-73
- DefSim: CMOS Defects on Chip for Research and EducationWitold A. Pleskacz, Tomasz Borejko, A. Walkanis, Viera Stopjaková, Artur Jutman, Raimund Ubar. 74-79
- FPGA-based Stuck-at Fault Emulation in Wavelet-based Image Coding SystemsLucía Costas, Juan Jose Rodríguez-Andina, Elena Lago. 83-87
- Exploring and Interpreting System Event LogsJanusz Sosnowski, Marek Poleszak. 91-96
- Fault Simulation with Parallel Critical Path Tracing for Combinatorial Circuits Using Structurally Synthesized BDDsSergei Devadze, Jaan Raik, Artur Jutman, Raimund Ubar. 97-102
- Using Multiple Clock Schemes and Multi-Temperature Test for Dynamic Fault Detection in Digital SystemsMarcial Jesús Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas 0001, Isabel C. Teixeira, João Paulo Teixeira 0001. 103-107
- Validation by Fault Injection of a Software Error Detection Technique Dealing with Critical Single Event UpsetsS. Torrellas, Bogdan Nicolescu, Raul Velazco, Mario García-Valderas, Yvon Savaria. 111-116
- SEU Effects Evaluation on a NoC Router ArchitectureArthur Pereira Frantz, Fernanda Lima Kastensmidt. 117-122
- Process Variation: Its Impact on the Design and Test of CMOS CircuitsKaushik Roy 0001. 123
- ATPG-based Techniques for VerificationDirhaj Pradhan. 125
- Parametric Failures and Detection StrategiesChuck Hawkins. 126
- An Optimal Test Assignment for Monitoring General Topology NetworksAndréa Weber, Elias Procópio Duarte Jr., Keiko V. O. Fonseca. 131-136
- Off-line Synchronization of Distributed Logs in Fault Injection Test CampaingsJoana M. F. da Trindade, Gabriela Jacques-Silva, Roberto Jung Drebes, Taisy Silva Weber, Ingrid Jansch-Pôrto. 137-142
- A New Approach to Cope with Single Event Upsets in Processor-based SystemsMassimiliano Schillaci, Matteo Sonza Reorda, Massimo Violante. 145-150
- Using Memory to Cope with Simultaneous Transient FaultsEduardo Luis Rhod, Carlos Arthur Lang Lisbôa, Luigi Carro. 151-156
- As Aspect-Oriented Fault Injection Tool to Test Fault Tolerant Mechanisms of Dependable Java-based Network ApplicationsKarina Kohl Silveira, Taisy Silva Weber. 159-164
- Modeling Software Reliability Growth with Artificial Neural NetworksGustavo A. de Souza, Silvia Regina Vergilio. 165-170
- Test Automation Viability Analysis MethodJorge Correa de Oliveira, Cidinha Costa Gouveia, Romulo Quidute Filho. 173-178
- Increasing Reliability in Future Technologies SystemsErik Schüler, Luigi Carro. 181-185
- Multiple Defect Tolerant Devices for Unreliable Future NanotechnologiesLorena Anghel, Cristiano Lazzari, Michael Nicolaidis. 186-191
- Probabilistic Error Correction in Linear Digital Filters Using Checksum CodesMaryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterjee. 192-197
- Observing SRAM-based FPGA Robustness in EMI-exposed EnvironmentsFabian Vargas 0001, Juliano Benfica, A. Farina, Eduardo Bezerra 0001, Edmundo Gatti, L. Garcia, D. Lupi, Fernando Hernandez. 201-206