Table of Contents

• Reliability and Yield: A Joint Defect-Oriented ApproachRoman Barsky, Israel A. Wagner. 2-10 [doi]
• On The Yield of Compiler-Based eSRAMsXiaopeng Wang, Marco Ottavi, Fred J. Meyer, Fabrizio Lombardi. 11-19 [doi]
• Failure Factor Based Yield Enhancement for SRAM DesignsYu-Tsao Hsing, Chih-Wea Wang, Ching-Wei Wu, Chih-Tsun Huang, Cheng-Wen Wu. 20-28 [doi]
• Defect Characterization for Scaling of QCA DevicesJing Huang, Mariam Momenzadeh, Mehdi Baradaran Tahoori, Fabrizio Lombardi. 30-38 [doi]
• A Highly Fault Tolerant PLA Architecture for Failure-Prone Nanometer CMOS and Novel Quantum Device TechnologiesAlexandre Schmid, Yusuf Leblebici. 39-47 [doi]
• Probabilistic Balancing of Fault Coverage and Test Cost in Combined Built-In Self-Test/Automated Test Equipment Testing EnvironmentShanrui Zhang, Minsu Choi, Nohpill Park, Fabrizio Lombardi. 48-56 [doi]
• Characteristics of Fault-Tolerant Photodiode and Photogate Active Pixel Sensor (APS)Michelle L. La Haye, Glenn H. Chapman, Cory Jung, Desmond Y. H. Cheung, Sunjaya Djaja, Benjamin Wang, Gary Liaw, Yves Audet. 58-66 [doi]
• Defect Avoidance in a 3-D Heterogeneous SensorGlenn H. Chapman, Vijay K. Jain, Shekhar Bhansali. 67-75 [doi]
• Co-Design and Refinement for Safety Critical SystemsAmmar Aljer, Philippe Devienne. 78-86 [doi]
• Noise Effects on Performance of Low Power Design Schemes in Deep Submicron RegimeMohamed Abbas, Makoto Ikeda, Kunihiro Asada. 87-95 [doi]
• On the Defect Tolerance of Nano-Scale Two-Dimensional CrossbarsJing Huang, Mehdi Baradaran Tahoori, Fabrizio Lombardi. 96-104 [doi]
• Monitoring Methodology for TID Damaging of SDRAM Devices based on Retention Time AnalysisStefano Bertazzoni, Domenico Di Giovenale, Marcello Salmeri, Arianna Mencattini, Adelio Salsano, M. Florean, Jeffery Wyss, Ricardo Rando, Silvano Lora. 106-110 [doi]
• Testing of Inter-Word Coupling Faults in Word-Oriented SRAMsXiaopeng Wang, Marco Ottavi, Fabrizio Lombardi. 111-119 [doi]
• Designs for Reducing Test Time of Distributed Small Embedded SRAMsBaosheng Wang, Yuejian Wu, André Ivanov. 120-128 [doi]
• An Efficient Hardware-Based Fault Diagnosis Scheme for AES: Performances and CostGuido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri. 130-138 [doi]
• A Fading Algorithm For Sequential Fault DiagnosisShi-Yu Huang. 139-147 [doi]
• Compression of VLSI Test Data by Arithmetic CodingHamidreza Hashempour, Fabrizio Lombardi. 150-157 [doi]
• Data Integrity Evaluations of Reed Solomon Codes for Storage SystemsGian-Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano. 158-164 [doi]
• An XOR Based Reed-Solomon Algorithm for Advanced RAID SystemsPing-Hsun Hsieh, Ing-Yi Chen, Yu-Ting Lin, Sy-Yen Kuo. 165-172 [doi]
• Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network ModelAjoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel. 174-182 [doi]
• Reducing Fault Latency in Concurrent On-Line Testing by Using Checking Functions over Internal LinesIrith Pomeranz, Sudhakar M. Reddy. 183-190 [doi]
• Victim Gate Crosstalk Fault ModelMichele Favalli. 191-199 [doi]
• Fast and Low-Cost Clock Deskew BufferMartin Omaña, Daniele Rossi, Cecilia Metra. 202-210 [doi]
• Dynamic Input Match Correction in RF Low Noise AmplifiersTejasvi Das, Anand Gopalan, Clyde Washburn, P. R. Mukund. 211-219 [doi]
• Mixed Loopback BiST for RF Digital TransceiversJerzy Dabrowski, Javier Gonzalez Bayon. 220-228 [doi]
• Fault Diagnosis of Analog Circuits by Operation-Region Model and X-Y Zoning MethodYukiya Miura. 230-238 [doi]
• Robust Low-Cost Analog Signal Acquisition with Self-Test CapabilitiesAdão Antônio de Souza Jr., Luigi Carro. 239-247 [doi]
• Coupling Different Methodologies to Validate Obsolete MicroprocessorsLorena Anghel, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero, Raoul Velazco. 250-255 [doi]
• A New Approach to Linear Connections Building BIST Structure Based on CSTP StructureIreneusz Gosciniak. 256-263 [doi]
• Transient Current Testing of Dynamic CMOS CircuitsNajwa Aaraj, Anis Nazer, Ali Chehab, Ayman I. Kayssi. 264-271 [doi]
• IC HTOL Test Stress Condition OptimizationBrian Peng, Ing-Yi Chen, Sy-Yen Kuo, Colin Bolger. 272-279 [doi]
• Testing and Defect Tolerance: A Rent s Rule Based Analysis and Implications on NanoelectronicsArvind Kumar, Sandip Tiwari. 280-288 [doi]
• Arithmetic Operators Robust to Multiple Simultaneous UpsetsCarlos Arthur Lang Lisbôa, Luigi Carro. 289-297 [doi]
• Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional CodesYinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra. 298-305 [doi]
• An Efficient Perfect Algorithm for Memory Repair ProblemsHung-Yau Lin, Fu-Min Yeh, Ing-Yi Chen, Sy-Yen Kuo. 306-313 [doi]
• First Level Hold: A Novel Low-Overhead Delay Fault Testing TechniqueSwarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy. 314-315 [doi]
• Error-Resilient Test Data Compression Using Tunstall CodesHamidreza Hashempour, Luca Schiano, Fabrizio Lombardi. 316-323 [doi]
• Online Testable Reversible Logic Circuit Design using NAND BlocksD. P. Vasudevan, Parag K. Lala, James Patrick Parkerson. 324-331 [doi]
• Toggle-Masking for Test-per-Scan VLSI CircuitsNitin Parimi, Xiaoling Sun. 332-338 [doi]
• Learning Based on Fault Injection and Weight Restriction for Fault-Tolerant Hopfield Neural NetworksNaotake Kamiura, Teijiro Isokawa, Nobuyuki Matsui. 339-346 [doi]
• Nonvolatile Repair Caches Repair Embedded SRAM and New Nonvolatile MemoriesJohn Y. Fong, Randy Acklin, John Roscher, Feng Li, Cindy Laird, Cezary Pietrzyk. 347-355 [doi]
• Modeling Yield of Carbon-Nanotube/Silicon-Nanowire FET-Based Nanoarray Architecture with h-hot Addressing SchemeShanrui Zhang, Minsu Choi, Nohpill Park. 356-364 [doi]
• Annotated Bit Flip Fault ModelMichele Favalli. 366-376 [doi]
• At-Speed Functional Verification of Programmable DevicesNicola Bombieri, Franco Fummi, Graziano Pravadelli. 386-394 [doi]
• Incorporating Signature-Monitoring Technique in VLIW ProcessorsYung-Yuan Chen, Kun-Feng Chen. 395-402 [doi]
• Exploiting an I-IP for In-Field SOC TestPaolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda. 404-412 [doi]
• Non-Intrusive Test Compression for SOC Using Embedded FPGA CoreGang Zeng, Hideo Ito. 413-421 [doi]
• On-Line Analysis and Perturbation of CAN NetworksMatteo Sonza Reorda, Massimo Violante. 424-432 [doi]
• Reliable System Co-Design: The FIR Case StudyCristiana Bolchini, Antonio Miele, Fabio Salice, Donatella Sciuto, Luigi Pomante. 433-441 [doi]
• Reliability Modeling and Assurance of Clockless Wave PipelineT. Feng, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi, Fred J. Meyer. 442-450 [doi]
• System-Level Dependability Analysis with RT-Level Fault Injection AccuracyRégis Leveugle, D. Cimonnet, Abdelaziz Ammari. 451-458 [doi]
• A Preliminary Investigation of Observation Diversity for Enhancing Fortuitous Detection of DefectsJennifer Dworak, James Wingfield, M. Ray Mercer. 460-468 [doi]
• Concurrent On-Line Testing of Identical Circuits Through Output Comparison Using Non-Identical Input VectorsIrith Pomeranz, Sudhakar M. Reddy. 469-476 [doi]
• An Application-Independent Delay Testing Methodology for Island-Style FPGAYen-Lin Peng, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu. 478-486 [doi]
• Concurrent Error Detection in Sequential Circuits Implemented Using Embedded Memory of LUT-Based FPGAsAndrzej Krasniewski. 487-495 [doi]
• Reconfiguration Algorithm for Degradable Processor Arrays Based on Row and Column ReroutingMasaru Fukushi, Susumu Horiguchi. 496-504 [doi]